Wiring structure of a semiconductor integrated circuit and a method of forming the wiring structure

ABSTRACT

A wiring structure for effectively reducing wiring capacitance, and a method of forming the wiring structure is disclosed. An underlying film having a dielectric constant lower than that of silicon oxide is formed on at least side surfaces of the wires of a wiring layer and a low dielectric constant film having an even lower dielectric constant is formed between the wires. Further, the surfaces of the underlying film are positively sloped. Because the low dielectric constants of the underlying film and the low dielectric constant film, wiring capacitance is effectively reduced. Further, the positively sloped surfaces facilitate the filling of narrow spaces between the wires by the low dielectric constant film.

BACKGROUND OF THE INVENTION

1. Field of Invention

This invention relates to a wiring structure for use in a semiconductorintegrated circuit in which wiring capacitance is effectively reducedand operational speed is improved and a method of forming the wiringstructure. This invention also relates to a semiconductor integratedcircuit in which the advantages of a low resistance wiring are fullyutilized while production and development costs are minimized.

2. Description of Related Art

Historically, in a semiconductor integrated circuit, as the designparameters or minimum feature sizes have been reduced by improvedfabrication technologies, both the number of elements which can beintegrated in a semiconductor chip and the operational speed have beenimproved. The main reason for improved operational speed is that theswitching speed of transistors has been improved as the dimensions i.e.,the gate length in the case of a MOS transistor, have been reduced.

However, if the design rule, usually expressed by the minimum gatelength of a transistor, becomes less than about 0.5 μm, the sizereduction of this feature does not always ensure improved operationalspeed. The main reason for this is that signal propagation time overlong distance wiring between circuit blocks within an integrated circuitchip tends to increase as the feature size decreases.

In other words, the resistance per unit length increases as the featuresize decreases because of the decrease in the cross-sectional area ofthe wiring. In addition, the capacitance per unit length also increasesas the feature size decreases because the space between wires is reducedwhile the height of the wires is kept almost constant. Also, thedimensions of the chip tends to increase as the design rule decreasesbecause the number of transistors integrated onto the chip increasesmore rapidly compared to the decrease in the size of the transistor.Therefore, the average wiring length between the circuit blocks tends toincrease as the design rule decreases. Accordingly, as feature sizedecreases the resistance of the wire and the capacitance between thewires increases, and the signal propagation time over the wiring betweencircuit blocks, which is roughly determined by the product of theresistance and the capacitance, tends to increase. Therefore, in orderto improve the operational speed of a semiconductor integrated circuit,in particular, in a semiconductor integrated circuit with a design sizeof 0.5 μm or less, the resistance of the wire and the capacitancebetween the wires needs to be reduced.

Conventionally, wiring mainly formed of aluminum or aluminum alloys(hereafter “aluminum-based wiring”) was used for metal wiring insemiconductor integrated circuits. Silicon oxide formed by chemicalvapor deposition (CVD) is generally used as a dielectric layer for theinsulation between wires in the same wiring layer and for the insulationbetween upper and lower wiring layers. Pure silicon oxide has adielectric constant of 3.9, while silicon oxide formed by CVD generallyhas a dielectric constant of approximately 4.0-4.4. The dielectric layerfor the insulation between wiring layers is referred to as the“interlayer dielectric layer”, while the dielectric layer for theinsulation between wires in the same wiring layer is referred to as the“intra-layer dielectric layer”, when it is necessary to distinguishbetween these two dielectric layers. However, these dielectric layersare usually formed integrally, and are usually collectively referred toas the “interlayer dielectric layer”.

In order to reduce wiring capacitance, use of insulating materialshaving lower dielectric constants than that of silicon oxide has beenconsidered. At the same time, in order to reduce the wiring resistance,use of wiring mainly formed of metals having resistivities lower thanthat of aluminum, such as silver, copper and gold has been considered.Among them, wiring mainly formed of copper or copper alloy (hereafter“copper-based wiring”) has been widely investigated.

Aluminum-based wiring is usually formed by depositing a metal film onthe entire surface of an insulating layer followed by selectivelyetching unnecessary portions of the metal film (hereafter “etchingmethod”). In contrast, formation of copper-based wiring by forminggrooves in a dielectric layer, followed by forming a copper or copperalloy film within the grooves, (hereafter “damascene method”) has beenexamined. (M. T. Bohr, IEEE International Electrons Devices MeetingDigest of Technical Papers (1995) p. 241, J. Paraszczak et al., IEEEInternational Electrons Devices Meeting Digest of Technical Papers(1993) p. 261).

The materials described below have been examined because they have lowerdielectric constants than silicon oxide.

1) Fluorinated Silicon Oxide

A technology has been developed in which a fluorinated silicon oxidefilm is formed by CVD using an atmosphere in which a fluorine compoundgas is added to a conventional silicon oxide CVD atmosphere. Thedielectric constant of the fluorinated silicon oxide film is about3.0-3.7, and it can be decreased by increasing the amount of addedfluorine. In practice, however, the dielectric constant can be loweredonly to about 3.3, since the film becomes hygroscopic if the amount ofadded fluorine is increased too much (H. Miyajima et al., Proceedings ofSymposium on Dry Process, (1994), p. 133, R. Katsumata et al.,Proceedings of Symposium on Dry Process, (1995), p. 269).

2) Siloxane SOG

For lower dielectric constant materials, various siloxane SOG(spin-on-glass) materials have been examined. In this technology, acoating solution which includes siloxane oligomers is coated on asubstrate and cured to form a SOG film. The siloxane oligomer includesSi—O and Si—R (R═H, CH₃, C₆H₅ etc.) bonds. The dielectric constant ofthe SOG film is about 2.8-3.3. For example, hydrogen silsesquioxane SOG(B. T. Ahlbum et al., Proceedings of the 1^(st) InternationalDielectrics for ULSI Multi-level Interconnection Conference (1995) p.36) and methyl-siloxane SOG (K. Numata et al., Materials ResearchSociety Symposium Proceedings, Vol. 381 (1995) p. 255) have been widelyexamined.

3) Organic Material

Organic materials, such as: polyimides, including BPDA-PDA, fluorinatedpolyimide, polyimide siloxane, fluorinated resin/siloxane copolymer,benzocyclobutene, parylene-F, poly(fluorinated naphthalane), amorphousTeflon™, fluorinated poly(arylethers), cyclo-perfluorocarbon polymer,and fluorinated amorphous carbon have been examined as low dielectricconstant materials. Many of these materials are formed by a coatingmethod, such as spin coating. However, some of these materials, e.g.,fluorinated amorphous carbon, are formed by CVD. See, for example, C. H.Ting et al., Materials Research Society Proceedings, Val. 381 (1995) p.3 C.-1, Lang et al., Materials Research Society Proceedings, Val. 381(1995) p. 45, M. Mills et al., 1^(st) International Dielectrics for ULSIMultilevel Interconnection Conference (1995) p. 269, S.-P. Jeng et al.,Materials Research Society Symposium proceedings, Val. 381 (1995) p.197, B. C. Auman, 1^(st) International Dielectrics for ULSI MultilevelInterconnection Conference (1995) p. 297, N. H. Hendricks et al., 1^(st)International Dielectrics for ULSI Multilevel Interconnection Conference(1995) p. 283, K. Endo et al., Japanese Journal of Applied Physics, Vol.35 (1996) p. 1348.

4) Porous Material

It is possible to decrease the dielectric constant by decreasing thedensity of the dielectric film. As an extreme example, a dielectricconstant of 1 can be obtained by providing a vacuum or an inert gasbetween wires. One method of decreasing the density is to form pores inthe dielectric film. For example, an organic porous material (K. R.Carter et al., Materials Research Society Symposium Proceedings. Vol 1.381 (1995) p. 79) or an inorganic porous material, such as a gel typesilica (U.S. Pat. No. 5,488,015), have been investigated. The latermaterial is often referred to as Xerogel™ or nano-porous silica. Adielectric constant of about 2.0 or below is reported. Another method isto remove a dielectric material which has been filled between the wires,after the wires and the dielectric material are formed. For example, amethod in which a carbon material formed between wires is removed byheating in oxygen is reported in M. B. Anand et al. Symposium on VLSITechnology Digest of Technical Papers (1996) p. 82.

Among the above-mentioned materials described in the categories 1)-4),the fluorine silicone oxide of category 1) has a lower limit dielectricconstant of about 3.3. Therefore, there is a limit in the ability toreduce the wiring capacitance. Accordingly, in order to reduce thecapacitance more effectively, further investigation of the materialscategorized above as 2), 3) and 4) are being pursued. Hereafter, when amaterial is simply called a “low dielectric constant material,” it meansabovedescribed materials except for the material of 1) category, andalso means other materials developed in the future having a dielectricconstant of around 3.0 or below.

Although the materials mentioned above which have low dielectricconstants have been extensively investigated, these materials aredifficult to utilize in semiconductor integrated circuits. First, thesematerials generally have a lower heat resistance than silicon oxide, andare susceptible to deformation or decomposition by heat processingduring the manufacturing process. Second, films of these materialsgenerally do not adhere onto the underlying metal film, or vise versa.Third, some of these materials contain relatively large amount of water.Even if the material does not initially contain a significant amount ofwater, the material may deform during heat processing and becomehygroscopic, thus adsorbing water during the subsequent processingsteps. This contained or adsorbed water may be desorbed during thesubsequent heat processing, and the desorbed water may cause variousproblems such as degradation of adhesion and metal corrosion. Fourth,the above-mentioned materials generally have lower mechanical strengthscompared to silicon oxide. Therefore, formation of hillocks on thesurface of the underlying metal film cannot be prevented.

Fifth, it is generally difficult to form via holes through which thelower wiring layer and the upper wiring layer are connected to eachother in films of these materials. In the case of the conventionalsilicon oxide film, via holes can be formed by aisotropical plasmaetching in a fluorine-based gas atmosphere using a resist as a maskfollowed by removing the resist mask by ashing, i.e., oxidation byactive oxygen or oxygen containing species created by plasma excitationor other methods. This method cannot generally be utilized for filmsformed of the materials described above because the etchingcharacteristics of many of these materials is similar to that of theresist. Therefore, a mask made of silicon oxide, silicon nitride oranother inorganic material film, instead of a resist mask, is often usedto form via holes in the film of a low dielectric constant material. Amask made of an inorganic material film is often referred to as a hardmask.

Even when a hard mask is utilized, a resist mask is used to formapertures in the hard mask. During removal of the resist mask used toform apertures in the hard mask, portions of the film at the aperturesare exposed to the ashing atmosphere. Many of the materials with lowdielectric constants tend to be easily oxidized by active oxygen in theashing atmosphere. The oxidation makes the material hygroscopic.Therefore, conditions for removal of the resist mask should be carefullychosen to suppress oxidation of the material. Some of the materials withlow dielectric constants can be etched using the resist mask. Even inthese cases, the conditions for removal of the resist mask should becarefully chosen to suppress oxidation of the surface of the materialexposed at the side walls of the via holes.

And sixth, the materials described above generally have low thermalconductivity compared to silicon oxide. Due to the low thermalconductivity, the joule heat produced in the wiring cannot beeffectively dissipated and the wiring may thermally breakdown under highpulsed current stress.

Furthermore, even if the materials described above having lowerdielectric constants are used, the wiring capacitance is not alwaysreduced effectively. That is, an effective dielectric constant, i.e., adielectric constant calculated from an actual capacitance value anddimensions of the wiring, does not always result in a reduced dielectricconstant for the material. For example, FIG. 1 shows wires 218 a, 218 band 218 c of a wiring layer 218 which are disposed on the surface of anunderlying dielectric layer 212 which is formed with a silicon oxidefilm deposited on a semiconductor substrate 210. In this case, eventhough an interlayer dielectric layer 220 of a material having a lowerdielectric constant is formed between and on the wires, the electricfield between the wires is not confined within the interlayer dielectriclayer 220. Rather, the electric field spreads into the underlyingdielectric layer 212, which is disposed immediately under the wiringlayer. Therefore, since the underlying dielectric layer 212 is formedwith a conventional silicon oxide film, the effective dielectricconstant between the wires is not reduced to the dielectric constant ofthe material used to form the interlayer dielectric layer 220. Thisphenomenon is described in U.S. Pat. No. 5,646,440.

In order to overcome at least some of the difficulties described abovefor materials having low dielectric constants, these materials are oftenused in combination with other insulating films, such as silicon oxide,silicon oxynitride, silicon nitride, or the like. For example, toimprove adhesion with an underlying wiring layer and to suppress hillockformation on the surface of the underlying metal film, an underlyingsilicon oxide film is first formed by CVD on the underlying wiring layerand then a low dielectric constant film is formed (J. T. Wetzel et al.,Materials Research Society Symposium proceedings Val. 381 (1995) P.217,Y. Homma et al., Proceedings of the 12^(st) International Conferenceon VLSI Multilevel Interconnection Conference (1995) p. 457). Thisunderlying film is also referred to as a liner film. Also, to improveadhesion of an upper wiring layer formed on an interlayer dielectriclayer and to prevent corrosion of the upper wiring layer by watercontained in the low dielectric constant film, an overlying film isformed on the low dielectric constant film. This overlying film is alsoreferred to as a cap film. The cap film may also used as the hard maskto form via holes in the interlayer dielectric layer.

However, the silicon oxide film deposited by CVD has a dielectricconstant of about 4.0 to 4.4. The silicon oxynitride or silicon nitridefilm has an even higher dielectric constant. Therefore, used of theunderlying and/or overlying film has an adverse effect on the ability toreduce wiring capacitance.

In addition, if the underlying film or the overlying film is depositedon a vertical surface by a conventional method such as plasma CVD, thesurface of the deposited film tends to overhang. For example, as shownin FIG. 2, if an underlying film 216 is deposited by a plasma CVD on asubstrate having a wiring layer 218 including wires 218 a, 218 b and 218c with vertical side surfaces, the surfaces of the deposited underlyingfilm 216 overhang on the side surfaces of the wires. The overhang of theunderlying film 216 makes the following processes difficult. Forexample, if a low dielectric constant film 228 is formed on thesubstrate with this underlying film, voids 229 are formed between thewires. The voids 229 cause cracks in the interlayer dielectric layer220. Further, the capacitance between the wires varies due to variationof the shape of the voids.

To overcome the difficulty of forming via holes in a low dielectricconstant film, a structure has been proposed in which a conventional CVDdielectric film is used for the insulation between adjacent wiringlayers, and the low dielectric constant material is used only for theinsulation between wires in the same wiring layer (S. P. Jeng et al.,Materials Research Society Symposium Proceedings, Vol. 337 (1994) p.25). However, in this case, the electric field between the wires spreadsinto the conventional CVD dielectric film having a relatively highdielectric constant formed on the wiring layer. Therefore, thecapacitance between the wires is even higher than the example shown inFIG. 1.

Forming a thermoconductive insulating layer, for example, a siliconnitride layer or an aluminum nitride layer, directly contacting thewires of a wiring layer to facilitate heat dissipation has beendescribed in U.S. Pat. No. 5,476,817. However, silicon nitride andaluminum nitride have even higher dielectric constant than siliconoxide. Therefore, in this case, since the electric field between thewiring significantly spreads into the thermoconductive insulating layerhaving a higher dielectric constant, the capacitance between the wiringbecomes even higher.

The previously mentioned U.S. Pat. No. 5,646,440 proposes a structure toeffectively reduce the capacitance between the wires by making thethickness of a low dielectric constant film between the wires greaterthan the height of the wires. However, the proposed structure also usesan underlying film of silicon oxide, silicon oxynitride or siliconnitride. Therefore, the problems described above related to theunderlying film are not overcome.

With respect to the wiring, it has been suggested that aluminum-basedwiring be completely replaced by copper-based wiring. However, variousproblems related to the copper-based wiring must be resolved in order tocost effectively produce semiconductor integrated circuits which utilizecopper-based wiring. A practical and economically feasible way toimplement copper-based wiring in various semiconductor integratedcircuit products has not been proposed.

SUMMARY OF THE INVENTION

In view of the aforementioned problems in the conventional systems, anobject of the invention is to provide a wiring structure whicheffectively reduces the capacitance between wiring as well as a methodof forming the wiring structure.

Another object of the invention is to provide a practical way toimplement low resistance wiring, such as copper-based wiring, insemiconductor integrated circuit products so that the advantages of thelow resistance wiring are fully utilized while the difficulties relatedto low resistance wiring are effectively overcome.

According to one aspect of the invention, a wiring structure for use ina semiconductor integrated circuit is provided which includes a wiringlayer with at least two adjacent wires formed on an underlyingdielectric layer over a semiconductor substrate, whereby the adjacentwires are disposed from each other with a space s1; and a dielectriclayer is formed on the wiring layer which includes a low dielectricconstant film having a dielectric constant lower than that of siliconoxide formed at least between opposing side surfaces of the adjacentwires such that the low dielectric constant film contacts the opposingside surfaces and wherein a bottom level of the low dielectric constantfilm between the adjacent wires is lower than a bottom level of theadjacent wires by at least about 20% of s1.

The invention also provides a method of forming a wiring structure foruse in a semiconductor integrated circuit which includes forming awiring layer, including at least two adjacent wires on an underlyingdielectric layer, over a semiconductor substrate, the adjacent wires aredisposed with a space of s1; and forming a dielectric layer on thewiring layer including forming a low dielectric constant film having adielectric constant lower than that of silicon oxide formed at leastbetween opposing side surfaces of the adjacent wires such that the lowdielectric constant film contacts the opposing side surfaces, and suchthat a bottom level of the low dielectric constant film between theadjacent wires is lower than a bottom level of the adjacent wires by atleast about 20% of s1.

According to another aspect of the invention, a wiring structure isprovided for use in a semiconductor integrated circuit which includes awiring layer including at least two adjacent wires formed on anunderlying dielectric layer formed over a semiconductor substrate; and adielectric layer including an underlying film having a dielectricconstant lower than that of silicon oxide formed at least on opposingside surfaces of the adjacent wires, and a low dielectric constant filmhaving a dielectric constant lower than that of the underlying filmformed at least between the opposing side surfaces of the adjacentwires.

The underlying film is preferably formed of fluorinated silicon oxide.The fluorinated silicon oxide may also contain substantially no Si(—F)₂bonds.

In addition, a bottom level of the low dielectric constant film betweenthe adjacent wires is lower than a bottom level of the adjacent wires.

A method of forming a wiring structure for use in a semiconductorintegrated circuit is provided which includes the steps of forming awiring layer, including at least two adjacent wires on an underlyingdielectric layer, over a semiconductor substrate; and forming adielectric layer including forming an underlying film having adielectric constant lower than that of silicon oxide at least onopposing side surfaces of the adjacent wires, and forming a lowdielectric constant film having a dielectric constant lower than that ofthe underlying film at least between the opposing side surfaces of theadjacent wires.

Preferably, forming the underlying film is performed by depositing afluorinated silicon oxide film by high density plasma CVD. The highdensity plasma CVD may be performed so that the fluorinated siliconoxide film contains substantially no Si(—F)₂ bonds.

According to another aspect of the invention, a wiring structure isprovided for use in a semiconductor integrated circuit which includes awiring layer including at least two adjacent wires formed on anunderlying dielectric layer formed over a semiconductor substrate; and adielectric layer including an underlying film formed at least onopposing side surfaces of the adjacent wires and a low dielectricconstant film having a dielectric constant lower than that of siliconoxide formed at least between the opposing side surfaces of the adjacentwires, wherein the opposing side surfaces of the adjacent wires aresubstantially vertical to a main surface of the semiconductor substrateand surfaces of the underlying film on the opposing side surfaces arepositively sloped.

Preferably, substantial portions of the surfaces of the underlying filmon the opposing side surfaces are positively sloped.

In addition, the underlying film is preferably formed of fluorinatedsilicon oxide having a dielectric constant lower than that of siliconoxide. The dielectric constant of the low dielectric constant film islower than that of the underlying film. The fluorinated silicon oxidemay include substantially no Si(—F)₂ bonds.

Preferably, the bottom level of the low dielectric constant film islower than that of the adjacent wires.

The invention also provides a method of forming a wiring structure foruse in a semiconductor integrated circuit which includes the steps offorming a wiring layer, including at least two adjacent wires on anunderlying dielectric layer, over a semiconductor substrate; and forminga dielectric layer including forming an underlying film at least onopposing side surfaces of the adjacent wires, and forming a lowdielectric constant film having a dielectric constant lower than that ofsilicon oxide at least between the opposing side surfaces of theadjacent wires, wherein the opposing side surfaces of the adjacent wiresare substantially vertical to a main surface of the semiconductorsubstrate, and surfaces of the underlying film on the opposing sidesurfaces are positively sloped.

The forming of an underlying film is preferably performed so thatsubstantial portions of the surfaces of the underlying film on theopposing side surfaces are positively sloped.

Also preferably, the forming an underlying film is performed by a highdensity plasma CVD with a substrate bias. In addition, the dielectricconstant of the low dielectric constant film is preferably lower thanthat of the underlying film, and the forming a low dielectric constantfilm is performed by a second high density plasma CVD with a substratebias.

According to another aspect of the invention, a wiring structure isprovided for use in a semiconductor integrated circuit which includes awiring layer which includes at least two adjacent wires formed on anunderlying dielectric layer over a semiconductor substrate; and adielectric layer including an underlying film formed at least onopposing side surfaces of the adjacent wires and a low dielectricconstant film having a dielectric constant lower than that of siliconoxide formed at least between the adjacent wires, wherein a thickness ofthe underlying film on upper portions of the opposing side surfaces ofthe adjacent wires is smaller than that on lower portions of theopposing side surfaces.

The underlying film is preferably formed of fluorinated silicon oxidehaving a dielectric constant lower than that of silicon oxide, and thedielectric constant of the low dielectric constant film is lower thanthat of the underlying film.

A method of forming a wiring structure for use in a semiconductorintegrated circuit is provided which includes the steps of forming awiring layer, including at least two adjacent wires on an underlyingdielectric layer, formed over a semiconductor substrate; and forming adielectric layer including forming an underlying film at least onopposing side surfaces of the adjacent wires, and forming a lowdielectric constant film having a dielectric constant lower than that ofsilicon oxide at least between the adjacent wires, wherein a thicknessof the underlying film on upper portions of the opposing side surfacesof the adjacent wires is smaller than that on lower portions of theopposing side surfaces.

The forming of an underlying film is preferably performed by a highdensity plasma CVD with a substrate bias.

Another aspect of the invention provides a wiring structure for use in asemiconductor integrated circuit which includes an intra-layerdielectric layer, including a low dielectric constant film having adielectric constant lower than that of silicon oxide, formed over asemiconductor substrate, the intra-layer dielectric layer having agroove formed in the low dielectric constant film; side wall filmshaving a second dielectric constant lower than that of silicon oxideformed on side walls of the groove; and a wiring layer including a wireformed in the groove.

The dielectric constant of the low dielectric constant film ispreferably lower than that of the side wall films.

Also preferably, the side walls films are formed of fluorinated siliconoxide. The fluorinated silicon oxide may include substantially noSi(—F)₂ bonds.

A method of forming a wiring structure for use in a semiconductorintegrated circuit is also provided which includes the steps of formingan intra-layer dielectric layer including a low dielectric constant filmhaving a dielectric constant lower than that of silicon oxide over asemiconductor substrate, the intra-layer dielectric layer having agroove formed in the low dielectric constant film; forming side wallfilms having a second dielectric constant lower than that of siliconoxide on side walls of the groove; and forming a wiring layer includinga wire formed in the groove.

Preferably, the dielectric constant of the low dielectric constant filmis lower than that of the side wall films.

Also preferably, the forming of side wall films includes depositing afluorinated silicon oxide film by high density plasma CVD. The highdensity plasma CVD deposition step may be performed such that thefluorinated silicon oxide film contains substantially no Si(—F)₂ bonds.

According to another aspect of the invention, a wiring structure isprovided for use in a semiconductor integrated circuit which includes anintra-layer dielectric layer including a low dielectric constant filmhaving a dielectric constant lower than that of silicon oxide formedover a semiconductor substrate, the intra-layer dielectric layer havinga groove formed in the low dielectric constant film; side wall filmsformed on side walls of the groove; and a wiring layer including a wireformed in the groove, wherein the side walls of the groove aresubstantially vertical with respect to a main surface of thesemiconductor substrate, and surfaces of the side wall films arepositively sloped.

Substantial portions of the surfaces of the side wall films arepreferably positively sloped.

Also preferably, the dielectric constant of the side wall films is lowerthan that of silicon oxide.

In addition, the side walls films are preferably formed of fluorinatedsilicon oxide. The fluorinated silicon oxide may include substantiallyno Si(—F)₂ bonds.

A method of forming a wiring structure for use in a semiconductorintegrated circuit is also provided which includes the steps of formingan intra-layer dielectric layer comprising a low dielectric constantfilm having a dielectric constant lower than that of silicon oxide overa surface of a semiconductor substrate, the intra-layer dielectric layerhaving a groove formed in the low dielectric constant film; forming sidewall films on side walls of the groove; and forming a wiring layerincluding a wire in the groove, wherein the side walls of the groove aresubstantially vertical with respect to a main surface of thesemiconductor substrate, and surfaces of the side wall films arepositively sloped.

Substantial portions of the surfaces of the side wall films arepreferably positively sloped.

The step of forming side wall films also preferably includes performinghigh density plasma CVD with a substrate bias. The step of forming awiring layer includes forming at least one of a barrier layer and a seedlayer by ionized sputtering.

The dielectric constant of the side wall films is preferably lower thanthat of silicon oxide.

According to another aspect of the invention, a wiring structure isprovided for use in a semiconductor integrated circuit which includes anintra-layer dielectric layer including a low dielectric constant filmhaving a dielectric constant lower than that of silicon oxide formedover a semiconductor substrate, the intra-layer dielectric layer havinga groove formed in the low dielectric constant film; side wall filmsformed on side walls of the groove; and a wiring layer including a wireformed in the groove, wherein a thickness of the side wall films onupper portions of the side walls of the groove is smaller than that onlower portions of the side walls.

A dielectric constant of the side wall films is preferably lower thanthat of silicon oxide.

The side walls films are preferably formed of fluorinated silicon oxide.

A method of forming a wiring structure for use in a semiconductorintegrated circuit is also provided which includes forming anintra-layer dielectric layer including a low dielectric constant filmhaving a dielectric constant lower than that of silicon oxide over asemiconductor substrate, the intra-layer dielectric layer having agroove formed in the low dielectric constant film; forming side wallfilms on side walls of the groove; and forming a wiring layer includinga wire in the groove, wherein a thickness of the side wall films onupper portions of the side walls of the groove is smaller than that onlower portions of the side walls.

The forming step includes the step of forming side wall films by highdensity plasma CVD with a substrate bias.

The dielectric constant of the side wall films is preferably lower thanthat of silicon oxide.

According to another aspect of the invention, a semiconductor integratedcircuit is provided which includes at least one aluminum-based wiringlayer disposed over a semiconductor substrate; at least one lowresistance wiring layer disposed over the at least one aluminum-basedwiring layer; and at least one circuit block including a plurality oftransistors disposed on the semiconductor substrate connected with eachother by wires in the at least one aluminum-based wiring layer, whereinwires of a selected type of wiring are formed on the at least one lowresistance wiring layer.

The selected type of wiring includes a long distance signal wiringconnecting the circuit block to an I/O cell or to a second circuitblock.

Also, the selected type of wiring preferably includes a portion of powerbus wiring commonly provided for supplying electric power to substantialportion of the integrated circuit.

In addition, the selected type of wiring may include a portion of powerbus wiring provided for improving current conduction capability of acorresponding portion of the power bus wiring formed on the at least onealuminum-based wiring layer.

The at least one circuit block also preferably includes a plurality ofcircuit blocks, and the selected type of wiring includes a portion ofclock wiring commonly provided for delivering a clock signal to theplurality of circuit blocks.

The circuit block may preferably include at least one macro cellselected from a macro cell library. Further, the macro cell library maybe developed without using a low resistance wiring.

The circuit block may include at least one macro cell which has beendesigned and verified without using a low resistance wiring.

The low resistance wiring layer may preferably be a copper-based wiringlayer.

The at least one low resistance wiring layer preferably includes atleast one pair of low resistance wiring layers that are provided forforming wires in mutually orthogonal directions.

A method of forming a semiconductor integrated circuit is also providedwhich includes the steps of forming at least one circuit block includinga plurality of transistors disposed on a semiconductor substrateconnected with each other by wires on at least one aluminum-based wiringlayer disposed over the semiconductor substrate; and forming wires of aselected type of wiring on at least one low resistance wiring layerdisposed over the at least one aluminum-based wiring layer.

According to another aspect of the invention, a semiconductor integratedcircuit is provided which includes at least one aluminum-based wiringdisposed over a semiconductor substrate; at least one low resistancewiring layer disposed over the at least one aluminum-based wiring layer;and at least one macro cell which has been designed and verified withoutusing a low resistance wiring.

The macro cell can preferably be placed into the system described abovewithout a substantial re-design.

The connections within the macro cell are mainly made by wires on the atleast one aluminum-based wiring layer, and connections outside of themacro cell are mainly made by wires on the at least one low resistancewiring layer.

The connections within the macro cell are preferably mainly made bywires on the at least one aluminum-based wiring layer, and wires of aselected type of wiring are formed on the at least one low resistancewiring layer.

A method of designing a semiconductor integrated circuit is providedwhich includes the steps of placing at least one macro cell which hasbeen designed and verified without using a low resistance wiring; andmaking connections outside of the macro cell mainly by wires on at leastone low resistance wiring layer.

The macro cell can preferably be placed without a substantial re-design.

The step of making connections preferably includes making wires of aselected type of wiring on the at least one low resistance wiring layer.

The step of making connections further includes making connectionswithin the macro cell mainly by wires on at least one aluminum-basedwiring layer.

According to another aspect of the invention, an application specificsemiconductor integrated circuit of one of a first and a second grade,is provided which includes at least one macro cell selected from a macrocell library commonly provided for the first and the second grade; andat least one aluminum-based wiring layer, wherein the semiconductorintegrated circuit further includes at least one low resistance wiringlayer only when the grade is a preselected one.

The macro cell library is preferably developed without using a lowresistance wiring.

The semiconductor integrated circuit also includes, if the grade is thepreselected one, at least one second macro cell selected from a secondmacro cell library provide only for the preselected one of the grades.

The invention further provides a method of designing an applicationspecific semiconductor integrated circuit of one of a first and a secondgrade, which includes the steps of selecting at least one macro cellfrom a macro cell library commonly provide for the first and the secondgrade; and placing the selected macro cell on the semiconductorintegrated circuit, wherein the method further comprises makingconnections outside of the macro cell by using wires on at least one lowresistance wiring layer only when the grade is a preselected one.

BRIEF DESCRIPTION OF THE DRAWINGS

The preferred embodiments of the invention will be described in detail,with reference to the following figures in which:

FIG. 1 is a cross-sectional view of a conventional wiring structure witha low dielectric constant film;

FIG. 2 is a cross-sectional view of a conventional wiring structure withan underlying film;

FIGS. 3A, 3B, 3C, 4D, and 4E are cross-sectional views showing theformation processes for the wiring structure according to the firstembodiment of the invention;

FIGS. 5A, 5B, 5C, 6D, 6E, and 6F are cross-sectional views showing theformation processes for the wiring structure according to the secondembodiment of the invention;

FIGS. 7A, 7B, 7C, 8D, 8E, 8F, 9G are cross-sectional views showing theformation processes for the wiring structure according to the thirdembodiment of the invention;

FIGS. 10, 10B, 10C, and 11D are cross-sectional views showing theformation processes for the wiring structure according to the fourthembodiment of the invention;

FIGS. 12A, 12B, 12C, and 13D are cross-sectional views showing theformation processes for the wiring structure according to the fifthembodiment of the invention;

FIGS. 14A, 14B, 14C, 15D, 15E, 15F, and 16G are cross-sectional viewsshowing the formation processes for the wiring structure according tothe sixth embodiment of the invention;

FIG. 17 is a cross-sectional view showing the formation process for thewiring structure according to an embodiment of the invention;

FIGS. 18A, 18B, 18C, 19D, 19E, 19F, 20G, 20H, 20I, and 21 arecross-sectional views showing the formation processes for the wiringstructure according to the seventh embodiment of the invention;

FIGS. 22A, 22B, 22C, 23D and 23E are cross-sectional views showing theformation processes of the wiring structure according to anotherembodiment of the invention;

FIGS. 24A, 24B, and 24C are cross-sectional views showing the formationprocesses for the wiring structure according to another embodiment ofthe invention;

FIGS. 25A, 25B and 25C are cross-sectional views showing the formationprocesses for the wiring structure according to the eighth embodiment ofthe invention;

FIGS. 26A and 26B are cross-sectional views showing examples of wiringlayer structures of products with and without Cu-based wiring layers;

FIG. 27 shows an example of a long distance signal wiring;

FIG. 28 shows an example of a clock wiring;

FIG. 29 shows an example of a power bus wiring; and

FIG. 30 shows an example of a signal wiring in a semiconductorintegrated circuit that has a DRAM and a logic circuit combined on thesame chip.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

This invention was first described in a Japanese application No.9-184888, hereby incorporated by reference.

Hereafter, based on the embodiments that are shown in the attacheddrawings, the wiring structure according to the invention, and a methodof forming the wiring structure according to the invention aredescribed. Further, a semiconductor integrated circuit according to theinvention is explained.

FIGS. 3A, 3B and 3C, and FIGS. 4D and 4F are cross sectional viewsshowing formation processes for a wiring structure according to thefirst embodiment of the invention.

In FIG. 3A, necessary structures for a semiconductor device, such astransistors and field oxides (not shown), are formed on the surface of asemiconductor substrate 10. An underlying dielectric layer 12 is firstformed by using, for example, a silicone oxide or BPSG (borophosphosilicate glass) film deposited by CVD, a silicon nitride film depositedby CVD, a SOG film, or a combination of these compounds over the surfaceof the semiconductor substrate 10.

The silicon oxide film and the BPSG film have dielectric constants ofabout 4.0-4.4. It is preferable to planarize the surface of theunderlying dielectric layer by a CMP (chemical mechanical polishing)method or the like.

Next, contact holes (not shown) for connecting transistors, which aredisposed on the surface of the semiconductor substrate, to wires of thefirst wiring layer are formed at necessary positions over the underlyingdielectric layer 12. Plugs of tungsten, for example, may be formed inthe contact holes, and a metal film 14 for forming wires of the firstwiring layer is deposited on the surface of the resulting substrate(hereafter, the term “substrate”, generally refers to a semiconductorsubstrate including a semiconductor substrate on which various layersand structures are formed). The metal film 14 has a laminated structureand may be formed by depositing, for example, a 10-50 nm thick titaniumfilm, a 30-150 nm thick titanium nitride film, a 300-1000 nm thickaluminum—0.5 wt % copper alloy film, a 5-20 nm titanium film, and a20-100 nm thick titanium nitride film, in this order. Variousaluminum-containing films, including pure aluminum film and variousaluminum alloy films, other than Al—0.5 wt % Cu film can be alsoemployed.

Next, as shown in FIG. 3B, a resist pattern 16 is formed usingconventional photolithography technology, and the metal film 14 ispatterned by an anisotropic plasma etching using a chlorine-based gasatmosphere (including, BCl₃, Cl₂ or the like), and a first wiring layer18 including wires 18 a, 18 b and 18 c is formed.

Various etching devices, such as for example, an ECR (electro-cyclotronresonance) plasma etching apparatus, a TCP (transformer coupled plasma)etching apparatus, or an ICP (inductive coupled plasma) etchingapparatus can be utilized. It is preferable to etch under conditionssuch that side surfaces of the wires 18 a, 18 b and 18 c aresubstantially perpendicular to a main surface of the semiconductorsubstrate. FIG. 3B shows a portion in which the wires of the firstwiring layer 18 are densely formed with a spacing of s1 between adjacentwires. The height of the wires of this portion is h1.

Next, as shown in FIG. 3C, the resist pattern 16 is removed byconventional etching technology. Further, surface portions of theunderlying dielectric layer 12 between the wires of the first wiringlayer 18 are etched to a depth of d1 by an anisotropic plasma etchingusing a fluorine-based gas atmosphere. It is preferable to etch underconditions such that the top titanium nitride film of the wires is notsubstantially etched. For the etching apparatus, a parallel-plate RIE(reactive ion etching) or an ICP etching apparatus, for example, can bepreferably utilized. Further, if necessary, an additional cleaningprocedure using a method such as ashing or wet cleaning is conducted.

Next, as shown in FIG. 4D, a fluorinated silicon oxide film is depositedby, for example, high density plasma CVD, and the surface of thedeposited film is then planarized by, for example, CMP to form ainterlayer dielectric layer 20. As an example, high density plasma CVDcan be performed using a helicon plasma CVD apparatus using a gasatmosphere including SiH₄, SiF₄, O₂ and Ar under the followingconditions where (Murota et al., Monthly Semiconductor World 1996. 2,p.82):

SiF₄:SiH₄=1:1

O₂/(SiF₄+SiH₄)=1-2

Ar/(SiF₄+SiH₄)=1

Substrate temperature=400° C.

Helicon plasma power (13.56 MHz)=2.5 Kw

Bias power (400 kHz)=2 kW

The dielectric constant of the fluorinated silicon oxide film is lowerthan that of pure silicon oxide. For example, it has a dielectricconstant of about 3.5. Moreover, under above-mentioned conditions, thefluorinated silicon oxide film can fill narrow spaces between wiresbecause deposition by CVD and etching by Ar sputtering proceedsimultaneously.

In the wiring structure according to this embodiment, the interlayerdielectric layer 20 is formed of a fluorinated silicon oxide having adielectric constant lower than that of silicon oxide. In addition,portions of the underlying dielectric layer 12 between the wires of thewiring layer 18 are etched to the depth of d1. Therefore, the depth ofthe interlayer dielectric layer 20 is lower than the depth of the wiresof the wiring layer 18. Further, the fluorinated silicon oxide filmfills the entire space between the wires with no underlying film. As aresult, the electric field between the wires is effectively confinedwithin the fluorinated silicon oxide film which has a low dielectricconstant. Therefore, the effective dielectric constant between the wiresis lowered to a value close to the dielectric constant of thefluorinated silicon oxide film itself, and the capacitance between thewires can be effectively reduced.

The capacitance can be effectively reduced especially when the depth d1is more than about 20% larger than the space s1. For example, when thespaces s1 are 0.50, 0.35, 0.25 and 0.18 μm, the respective depths d1 areabout 0.1, 0.07, 0.05 and 0.036 μm. The capacitance can be furtherreduced when the depth d1 is more than about 50% larger than thedistance of s1. For example, when the spaces s1 are 0.50, 0.35, 0.25,0.18 μm, the respective depths d1 are about 0.25, 0.18, 0.12 and 0.09μm.

When the fluorinated silicon oxide film is deposited by high densityplasma CVD under appropriate conditions, the film is of sufficientlyhigh quality to allow direct contact with the wires. Specifically, Si—Fbonds in the fluorinated silicon oxide film make the film hydrophobic.As a result, the water content in the fluorinated silicon oxide film issufficiently low. However, when the fluorine content in the fluorinatedsilicon oxide film becomes too large, the content of Si(—F)₂ bondsincreases and the film becomes hygroscopic. Therefore, the fluorinecontent in the fluorinated silicon oxide film should be limited to therage in which the amount of Si(—F)₂ bonds in the film is sufficientlylow. That is, intensity of an FTIR (Fourier transformed infraredabsorption spectroscopy) absorption peak by Si(—F)₂ bonds (appearsaround 980 cm⁻²) should negligibly small, or integrated intensity of theabsorption peak by Si(—F)₂ bonds is less than about 0.2%, or preferablyless than about 0.1% of integrated intensity of an absorption peak bySi—O bonds (appears around 1080 cm⁻²). This limitation in the fluorinecontent limits the dielectric constant of the fluorinated silicon oxidefilm. Using currently available high density plasma CVD technology, thelower limit of the dielectric constant is about 3.3. However, futureadvancement in the film formation technology may allow further reductionof the dielectric constant without substantially increasing the contentof Si(—F)₂ bonds.

If it is necessary, the same process is repeated, and second andsubsequent wiring layers and interlayer dielectric layers are formed.

FIG. 4E shows a cross sectional view whereby a second wiring layer 22,which includes wires 22 a, 22 b and 22 c, and a second interlayerdielectric layer 24 are formed. In the wiring structure shown in FIG.4E, the first interlayer dielectric layer 20 mutually insulates thewires of the first wiring layer 18, and also insulates the first wiringlayer 18 and the second wiring layer 22. The thickness of the interlayerdielectric layer 20 between the wiring layer 18 and 22 is approximately0.6-1.5 μm. Although not shown in the drawings, via holes for connectingthe wires of the first wiring layer 18 and the wires of the secondwiring layer 22 are formed at necessary positions over the interlayerdielectric layer 20. Plugs which fill the via holes are formed by, forexample, CVD and etch back of a tungsten film. According to thisembodiment, via holes can be formed by a conventional method, in theinterlayer dielectric layer 20 formed by a fluorinated silicon oxidefilm which is deposited by using a high density plasma CVD method, aslong as the fluorine content of the film is limited within anappropriate range.

Finally, a passivation layer and bonding pads are formed and the wafermanufacturing process for the semiconductor integrated circuit iscompleted. When the second wiring layer 22 is the top wiring layer, thepassivation layer is directly formed thereon.

In FIG. 3 and FIG. 4, portions of the underlying dielectric layer 20between the wires of the first wiring layer 18 are completely etched tothe depth of d1 in a rectangular shape. In practice, it is difficult toetch in a completely rectangular shape, and it is not necessary fordevice operation. For example, it is appropriate to etch the peripheralportions in a curved or rounded shape. In this case, the depth d1 ismeasured at the central portion between the wires. It is also acceptableto use isotropic etching to etch the surface portions of the underlyingdielectric layer. In this case, the etching also proceeds in thehorizontal direction under the wires and the surface portions of theunderlying dielectric layer 12 are etched in a concave shape. By doingthis, there is the advantage that the effect of confining the electricfield between the wires of the first wiring layer 18 in the fluorinatedsilicon oxide becomes higher, and the effect of reducing the capacitancebetween the wires becomes even higher.

Moreover, depending on the flatness of the surface of the underlyingdielectric layer 12, there are cases when the bottom levels of theadjacent wires are not matched. In this case, the difference in depthbetween the bottom level of the fluorine silicon oxide film and thebottom level of the wire can be determined from the difference betweenthe bottom level of the fluorine silicon oxide film at the centralportion between the wires and the average depth of the lower levels ofthe adjacent wires.

According to this embodiment, after etching of the metal film 14,etching of the surface portions of the underlying dielectric layer 12 isperformed after removing the resist pattern 16 by a plasma etching whichis separate from the etching of the metal film 14. However, theinvention is not limited to this technique. For example, by increasingthe over-etching period of the etching of the metal layer 14, it ispossible to also etch the surface portions of the underlying dielectriclayer 12. This over-etching is effective for removing etching residueswhich are caused, for example, by silicon precipitation in the metalfilm 14.

According to this embodiment, the interlayer dielectric layer 20 isformed by a fluorinated silicone oxide film deposited by using a heliconplasma CVD method. However, the invention is not limited to this method.It is also possible to use other high density plasma CVD methods such asICP-CVD, ECR-CVD or the like. Further, the example of using a CVD gasatmosphere including SiH₄, SiF₄, O₂ and Ar is illustrative. However, itis possible to use a CVD atmosphere including Si₂F₅, SiH₃F, SiH₂F₂,SiHF₃ or the like. It is also possible to use a fluorine compound gassuch as CF₄, C₂F₆, NF₃ or the like as the fluorine compound gas. In thiscase, as a silicon raw material, it is also possible to usenon-fluorinated silicon compound gas only. Conversely, it is alsopossible to use a fluorinated silicon compound gas as a Si raw materialwithout mixing it with a non-fluorinated silicon compound gas. It isalso possible to use an organic silicon compound gas such as Si(OC₂H₅)₄or the like as a silicon raw material. It is also possible to use afluorinated organic silicon compound gas such as FSi(OC₂H₅)₃,F₂Si(OC₂H₅)₂ or the like.

The fluorinated silicon oxide film may also be formed by a conventionalplasma CVD method instead of the high density plasma CVD method.However, in this case, the lower limit of the dielectric constant whichcan preserve low hygroscopicity is higher than the case when a highdensity plasma CVD method is used.

Moreover, it is possible to form the interlayer dielectric layer 20 byusing materials other than fluorinated silicon oxide. Other materialswhich have lower dielectric constants than that of silicon oxide, forexample, SIBON and the like which can be formed by plasma CVD, can beused. Further, if problems, such as poor adhesion and water absorptionare solved, it is obviously possible to use various kinds of lowdielectric constant materials such as siloxane SOG, organic materials,porous materials and the like.

According to this embodiment, an aluminum-based wiring which mainlyformed of an aluminum containing film is used to form the first andsecond wiring layers 18 and 22. However, the invention is not limited tothis method. Wiring of different materials can be used to form one orboth of the wiring layers. For example, a copper-based wiring or awiring which mainly formed of tungsten film (tungsten-based wiring) canbe used. Moreover, it is possible to form the first wiring layer 18 andthe interlayer dielectric layer 20 by the above-mentioned method afterother wiring layers are formed below the first wiring layer 18.

According to this embodiment, the dielectric layer 12 below the firstwiring layer 18 is called an “underlying dielectric layer,” and thedielectric layer 20 between the first wiring layer 18 and the secondwiring layer 22 is called an “interlayer dielectric layer.” However,these terms should not be interpreted narrowly. The dielectric layer 12below the first wiring layer 18 not only functions as an “underlyingdielectric layer” for the first wiring layer 18, but also finctions asan “interlayer dielectric layer” between the transistors, which areformed on the semiconductor substrate 10, and between the transistorsand the first wiring layer 18. Also, when other wiring layers are formedbeneath the first wiring layer 18, the dielectric layer 12 may functionas an “interlayer dielectric layer” between wires of these lower wiringlayers and between these lower layers and the first wiring layer.Similarly, the interlayer dielectric layer 20 also functions as an“underlying dielectric layer” for the second wiring layer 22.

FIGS. 5A, 5B and 5C and FIGS. 6D, 6E and 6F are cross sectional viewsshowing the formation processes for a wiring structure according to thesecond embodiment of the invention.

FIG. 5A shows an underlying dielectric layer 12 formed on asemiconductor substrate 10 and a first wiring layer 18, which includeswires 18 a, 18 b and 18 c formed on that underlying dielectric layer 12,as described in connection with the first embodiment. Similarly, theheight of the wires of the first wiring layer 18 is represented by h1,and the space between the wires is represented by s1. After this,surface portions of underlying dielectric layer 12 between the wires ofthe first wiring layer 18 are etched to a depth of d1.

Next, as shown in FIG. 5B, a fluorinated silicon oxide film is depositedby, for example, high density plasma CVD. In this embodiment, thedeposition time is set shorter than that of the first embodiment, andthe deposition is terminated when the top and side surfaces of the wiresare covered, before reaching a point at which the film fills the spacesbetween the wires of the first wiring layer 18. At this point, thethickness of the fluorinated silicon oxide film formed on the surface ofthe underlying dielectric layer 12 between the wires of the first wiringlayer 18 is t1, and the thickness on the top surfaces of the wires ist2. When the deposition time is set so as not to fill the spaces betweenthe wires, both t1 and t2 are approximately the same as the thickness ofthe film deposited on a bare substrate i.e., a substrate without anystructure formed thereon. By applying a radio frequency power to thesubstrate holder and generating a bias potential, deposition by CVD andetching by Ar sputter proceed simultaneously during the formation of thefluorinated silicon oxide film by the high density plasma CVD. As aresult, even when side surfaces of the wires of the first wiring layer18 are formed substantially vertical, substantial portions of surfacesof the fluorinated silicon oxide film on the side surfaces of the wiresare uniformly positively tapered, except for portions around top edgesof the wires. In other words, the thickness on upper portions of theside surfaces is thinner than that on lower portions of the side walls.Moreover, facets are formed on the top edges of the wires. The facetshave a certain angle, normally 45° to 60° with respect to the horizontalsurface which is determined by the angle dependency of the sputteretching rate.

This fluorinated silicon oxide film 13 becomes part of the interlayerdielectric layer, and becomes an underlying film 26 with respect to alow dielectric constant film which is formed in the next step.

Next, as shown in FIG. 5C, a coating solution which contains, forexample, siloxane oligomers is applied to the surface of substrate by aspin coating method and cured to form a low dielectric constant film 28.At this time, since the underlying film 26, which was formed by the highdensity plasma CVD, has tapered side surfaces and facetted top corners,remaining portions between the wires can be filled with the siloxane SOGeven when the spaces become very narrow. The cure can be accomplishedby, for example, a poly-condensation reaction which occurs by heating toabout 400° C., after the solvent which is contained in the coatingsolution is evaporated by heating to the temperatures of 80° C. and 200°C. The low dielectric constant film 28 formed by this method has adielectric constant of approximately 3.0.

The surface of the low dielectric constant film 28 at this stage has arelatively planarized shape compared to the surface of the underlyingfilm 26. For example, on areas in which wires are densely formed, asshown in the cross sectional view of FIG. 5C, the surface has a nearlyflattened shape. However, the surface of the low dielectric constantfilm is not globally planarized. That is, for example, the surface ofthe low dielectric constant film 28, which is deposited on areas inwhich wires are densely formed, is higher than the surface of the lowdielectric constant film 28 which is formed on areas in which wire isnot formed. To accomplish the global planarization, it is favorable tofurther planarize the surface by, for example, a CMP method.

As previously mentioned, the sloped side surfaces, facilitate thefilling of the low dielectric constant film between the wires,especially when the sloped side surfaces are combined with the facetedtop corners. The slope is preferably about 2° or more, more preferablyabout 4° or more, or most preferably about 6° or more with respect tothe normal of the main surface of the semiconductor substrate tosufficiently facilitate the filling. However, it is not preferable toincrease the slope too large, for example., more than about 8°. Thesmall slope ensures that substantial portions between the wires remainto be filled with the low dielectric constant film, and that thecapacitance between the wires is effectively reduced. The degree of theslope can be controlled by adjusting the deposition condition,especially, the substrate bias conditions of the high density plasmaCVD.

The sloped side surface is particularly effective to facilitate thefilling when particular methods are utilized to deposit the lowdielectric constant film. For example, low dielectric constant materialssuch as fluorinated amorphous carbon or the like can be preferablydeposited by high density plasma CVD with a substrate bias. Because ofthe similarity of the deposition methods of the underlying film and thelow dielectric constant film, the filling of narrow spaces between wiresby the low dielectric constant film can be effectively facilitated. Inthis case, it is also possible to deposit the underlying film and thelow dielectric constant film in the same deposition apparatus, i.e.,deposit the films in the same deposition chamber by changing the CVD gasatmosphere or deposit the films in separate deposition chambers of thesame apparatus.

FIG. 6D shows a cross sectional view in which CMP is performed until alow dielectric constant film 28 above the top surface of the firstwiring layer 18 is removed, while the film between the wires of thefirst wiring layer 18 remains. When the low dielectric constant film 28before the CMP process is sufficiently thick, the surface can beglobally planarized by the CMP. Specifically, when the thickness of thelow dielectric constant film 28 before the CMP process at portions inwhich no wire is formed is made to be approximately the same or greaterthan the total of the height h1 of the wiring and the etched depth d1 ofthe underlying dielectric layer 12 between the wires, or preferably 1.5times or more, or even more preferably 2.0 times or more thicker,sufficient global planarization can be achieved. For example, by using aslurry including MnO₂ abrasive, the low dielectric constant film 28 canbe polished with a higher speed compared to the underlying insulatingfilm 26 (Y. Homma et al., Proceedings of the 12^(th) InternationalConference on VLSI Multilevel Interconnection Conference (1995) p. 457).As a result, the fluorinated silicon oxide film which is the underlyingfilm 26 on top of the wires can be used as an etching stopper, and CMPcan be terminated at the point when the low dielectric constant film 28on the wiring is removed, with a high controllability.

Then, as shown in FIG. 6E, another fluorinated silicon oxide film isdeposited by high density plasma CVD, and a cap film 30 is formed. Byperforming the above-mentioned processes, an interlayer dielectric layer32, comprising the underlying film 26, the low dielectric constantmaterial film 28 which fills in between the wires and the cap film 30,is formed.

In the wiring structure according to this embodiment, a low dielectricconstant film 28 made of siloxane SOG, which is a low dielectricconstant material, is filled in between the wires of the first wiringlayer 18. The level of the bottom surface of this low dielectricconstant film 28 is lower than the level of the bottom surface of thewiring by an amount of (d1−t1), and the level of the top surface of thelow dielectric constant film is higher than the level of the top surfaceof the wiring by an amount of t2. Moreover, the underlying film 26 onthe side surfaces of the wires of the first wiring layer 18 and the capfilm 30 are formed by fluorinated silicon oxide film which has a lowerdielectric constant than silicon oxide. As a result, the capacitancebetween wires is effectively reduced.

The capacitance between the wires is determined by the dimensions of s1,h1, t1, t2 and the like and the dielectric constants of the fluorinatedsilicon oxide film and the siloxane SOG. Generally, the thinner the filmthickness of the underlying film 26, the more the capacitance betweenthe wires is reduced.

The underlying film 26 improves adhesion of the low dielectric constantfilm 28. It also has the function of preventing water contained in thelow dielectric constant film 28 from diffusing to the wires or to thetransistors which are disposed on the surface of the semiconductorsubstrate 10. With respect to the adhesion improvement, a sufficienteffect can be obtained as long as the underlying film 26 is continuouslyformed. On the other hand, in order to prevent water diffusion, acertain thickness of the underlying film 26 is necessary. A siliconoxide film which is deposited by a high density plasma CVD method, suchas disclosed in the U.S. Pat. No. 5,512,513, has a high water diffusionprevention effect. Because of this, a high water diffusion preventioneffect can be obtained even with a thin film thickness, compared to thecase in which the underlying film is deposited by other methods, such asconventional plasma CVD.

In conventional wiring structures, a film of silicon oxide, siliconoxynitride, silicon nitride or the like is used as the underlying film.In contrast, according to this embodiment, a fluorinated silicon oxidefilm is used as the underlying film 26 for the low dielectric constantfilm 28. As a result, the wiring capacitance can be further effectivelyreduced. It was not obvious that a fluorinated silicon oxide film couldbe used as an underlying film. It was also not clear that a fluorinatedsilicon oxide film has sufficient adhesion improvement effects and waterdiffusion prevention effects. In addition, is was not clear that theamount of water contained in the fluorinated silicon oxide film itselfis sufficiently low so that wires on which the fluorinated silicon oxidefilm is formed are not corroded. In practice, the addition of fluorinedoes not materially degrade the adhesion improvement effect. Also, theaddition of fluorine does not substantially degrade the water diffusionprevention effects nor does it increase the amount of water in the film.Further, Si—F bonds in the fluorinated silicon oxide film make the filmhydrophobic, and the water diffusion prevention effects are actuallyimproved and the amount of water in the film is actually decreased. As aresult, by using a fluorinated silicon oxide film rather than a siliconoxide film the thickness of the underlying film can be reduce. Forexample, t1 can be thinned to less than 25 nm, and can be thinned toaround 10 nm, depending on various conditions. Accordingly, it ispossible to use this method even when the space between the wires isfurther decreased due to the progress of miniaturization.

Note that, however, the fluorine content in the fluorinated siliconoxide film should not be increased too much so that the film does notsubstantially contain Si(—F)₂ bonds. Because of this, the dielectricconstant of the underlying film 26 cannot be decreased below a certainvalue. However, the wiring capacitance can be effectively reduced bycombining the low dielectric constant film with a material having adielectric constant lower than that of the fluorinated silicon oxide.Because the wires are covered with the underlying film having a highwater diffusion prevention ability, various low dielectric constantmaterials can be used to form the low dielectric constant film 28.

According to this embodiment, it is preferable to make the etching depthd1 of the underlying dielectric layer 12 larger in comparison to thelayer described in connection with the first embodiment by the amount oft1 so that the bottom level of the low dielectric constant film 28 issufficiently lower than the bottom level of the wires. However, evenwhen the depth d1 is not sufficiently large, or even when the surfaceportions of the underlying dielectric layer 12 is not etched, wiringcapacitance can be reduced to some extent because both the underlyingfilm 26 and the low dielectric film is formed with materials havinglower dielectric constants.

After this, the same process is repeated as necessary, to form thesecond and subsequent wiring layers and interlayer dielectric layers. Across-sectional view of FIG. 6F shows a structure including a secondwiring layer 22 containing wires 22 a, 22 b and 22 c, and a secondinterlayer dielectric layer 40 which includes an underlying film 34, alow dielectric constant film 36 which fills in between the wires of thesecond wiring layer 22, and a cap film 38 formed over the low dielectricconstant film 36.

Then, a passivation layer and bonding pads are formed, and the wafermanufacturing process of the semiconductor integrated circuit iscompleted.

According to this embodiment, the cap film 30 is made of a fluorinatedsilicon oxide film and is used for the insulation between the wiringlayers 18 and 22. Via holes which connect between the wiring layers 18and 22 are formed in the cap film 30. Therefore, it is possible to formvia holes by the same method as when the interlayer dielectric layer isformed by using a conventional silicon oxide film. Moreover, adhesion ofthe wires of the second wiring layer 22, which is formed on the. surfaceof the cap film 30, is comparable to the case when the wires are formedon a conventional silicon oxide film. Additionally, since thefluorinated silicon oxide film has a lower dielectric constant than thatof conventional silicon oxide film, the capacitance between the wiringlayers 18 and 22 can be effectively reduced. Accordingly, the wiringstructure of the present embodiment can effectively reduce thecapacitance between wires within a wiring layer and between differentwiring layers, and at the same time, can preserve compatibility withconventional manufacturing technology.

In the present embodiment, siloxane SOG is used to form the lowdielectric constant film 28. However, the present invention is notlimited to this, and other kinds of low dielectric constant materialscan also be used. For example, it is appropriate to use a low dielectricconstant material which has a dielectric constant of, for example, about3.2 or less, more preferably about 3.0 to 2.5 or less, and mostpreferably about 2.0 or less. Moreover, it is possible to form the lowdielectric constant film 28 by using a fluorinated silicon oxide film bya high density plasma CVD method. In this case, the depositionconditions are adjusted, and the dielectric constant is reduced to about3.2 or less, and preferably to about 3.0 or less by increasing thefluorine content compared to the case of forming the underlying film 26and the cap film 30. The film quality of the fluorinated silicon oxidefilm degrades when the fluorine content is increased. However, accordingto this embodiment, a fluorinated silicon oxide film with a highfluorine content can be used as the low dielectric constant film 12,because the low dielectric constant film does not directly contact thewires.

In this embodiment, a fluorinated silicon oxide film which is depositedby a high plasma CVD method is used for the cap film 30, and is used forthe insulation between the wiring layers 18 and 22. However, theinvention is not limited to this method. It is also possible to use asilicon oxide film. It is also possible to use a fluorine silicon oxidefilm which is deposited by a conventional plasma CVD method. However, inorder to decrease the wiring capacitance, it is preferable for the capfilm 30 to have a lower dielectric constant. To obtain this, it ispreferable to use a fluorinated silicon oxide film which is deposited byusing a high density plasma CVD method with which a dielectric constantof approximately 3.5 or less can be obtained while maintaining highquality.

In this embodiment, a fluorinated silicon oxide film, which is depositedby a high density plasma CVD method with a substrate bias, is used forthe underlying film 26. However, the invention is not limited to thismethod. In order to improve the filling ability of the low dielectricconstant film 28 in narrow spaces between wires, it is preferable thatthe surface of the underlying film is positively sloped. It is furtherpreferable that top corners of the underlying film are facetted.However, to improve the filling ability, the underlying film is notnecessarily made of a fluorinated silicon oxide film. For example, it isalso possible to use silicon oxide formed by, for example, high densityplasma CVD with a substrate bias. Also, deposition methods other thanhigh density plasma CVD can be used, as long as sloped side surfacesand/or facetted corners are deposited. Further, a film withoutpositively sloped side surfaces can be deposited by a conventionalplasma CVD or by a high density plasma CVD without substantial substratebias, and then the deposited film can be subject to a plasma etchingusing a non-reactive gas, such as Ar, or a reactive gas, such as C₂F₆,to form positively slopes side surfaces.

However, in order to effectively reduce the capacitance between thewiring, is preferable use a film having a dielectric constant lower thanthat of silicon oxide as the underlying film. In order to do so, it ispreferable to use a fluorinated silicon oxide film which is deposited byusing a high density plasma CVD, through which a film having adielectric constant of about 3.5 or less can be deposited whilemaintaining high film quality.

In this embodiment, it is also possible to form a cap film with a lowdielectric constant material. Forming the cap film with a low dielectricconstant material can further reduce the capacitance between the wiringlayers 18 and 22 and between the wires. In this case, it is possible touse the same low dielectric constant material as used for the lowdielectric constant film 28, or to use a different material. In order toform the low dielectric constant film 28 between the wires, it isnecessary to choose a material which can fill in narrow spaces and caneffectively planarize the surface. On the contrary, since the cap filmis formed after the surface is planarized by CMP of the low dielectricconstant film 28, a high filling ability and planarizing ability are notnecessary for the material to form the cap film 30. For example,materials having a lower dielectric constant and which are compatiblewith the via hole forming process are preferably used.

FIGS. 7A, 7B and 7C, FIGS. 8D, 8E and 8F and FIG. 9E are cross sectionalviews showing the formation processes for forming a wiring structureaccording to an embodiment of the invention.

As shown in FIG. 7A, an underlying dielectric layer 12 is formed byusing a BPSG film or the like on a semiconductor substrate 10, and ametal film 14 for forming the first wiring layer is deposited on thissubstrate similar to the method described in connection with the secondembodiment. Next, according to this embodiment, a silicon oxide film 42is formed on the metal film 14 by a plasma CVD method.

Then, as shown FIG. 7B, a resist pattern (not shown) is formed, andafter patterning the silicon oxide layer 42 by anisotropic plasmaetching using a fluorine-based gas atmosphere, the resist pattern isremoved by ashing. Next, the metal film 14 is patterned by ananisotropic plasma etching using a chlorine-based gas atmosphere, usingthe patterned silicon oxide film 42 as a mask. Then, the first wiringlayer 18 having wires 18 a, 18 b, 18 c is formed. Here, the height ofthe wires of the first wiring layer 18 is h1, and the space between thewires is s1.

Next, as shown in FIG. 7C, anisotropic plasma etching using afluorine-based gas atmosphere is performed to etch surface portions ofthe underlying dielectric layer 12 between the wires to a depth of d1.If necessary, substances on side walls of the wires which were depositedduring the metal etching are removed, for example, by ashing, beforeperforming the etching of the surface portions of the underlyingdielectric layer. The thickness of the silicon oxide film 42 on the topof the wires after this process is d2. Since the silicon oxide film 42on the wires is also partially etched during the etching of the surfaceportions of the underlying dielectric layer, deposition thickness of thesilicon oxide film 42 is set so that the necessary film thickness willremain.

Next, as shown in FIG. 8D, a fluorinated silicon oxide film is depositedby high density plasma CVD, and an underlying film 26 is formed. Similarto the second embodiment, the thickness of the underlying film 26 on theunderlying dielectric layer between the wires is t1, and the thicknesson the silicon oxide film 42 on the top of the wires is t2.

Next, as shown in FIG. 8E, a low dielectric constant film formed of asiloxane SOG is formed over the entire substrate surface, and CMP isperformed until the low dielectric constant film above the wires of thefirst wiring layer 18 is removed, thus forming a low dielectric constantfilm 28 which fills in between the wires. In order to obtainsufficiently planarized surface, it is preferable to make the lowdielectric constant film 28 before the CMP thicker than in the case ofthe second embodiment by an amount d2.

Next, as shown in FIG. 8F, a fluorinated silicon oxide film is formed byusing a high density plasma CVD, and a cap film 30 is formed. Throughthe above-mentioned processes, an interlayer dielectric layer 44 isformed, which includes the underlying film 26, the low dielectricconstant film 28 which fills in between the wires of the first wiringlayer 18, and the cap film 30.

In the wiring structure according to this embodiment, the lower level ofthe low dielectric constant film 28 which fills in between the wires ofthe first wiring layer 18 is bottom than the bottom level of the wiringby an amount (d1−t1), and additionally, the top level of the lowdielectric constant film 28 which fills in between the wires of thefirst wiring layer 18 is higher than the top level of the wires by anamount (t2+d2). Accordingly, the capacitance between the wires can befurther reduced compared to the structure of the second embodiment. Inorder to effectively reduce the capacitance between the wires, the valueof (t2+d2) should be about 20% or more, or preferably, about 50% or moreof the space s1.

After this process, the same process is repeated as necessary, and thesecond and subsequent wiring layers and interlayer dielectric layers areformed. In FIG. 9G, a second wiring layer 22 having wires 22 a, 22 b and22 c and the second interlayer dielectric layer 48, which includes anunderlying film 34, a low dielectric constant film 36 which fills inbetween the wires of the second wiring layer 22, and a cap film 38, areshown. A silicon oxide film 46 is also formed on the top of the wires ofthe second wiring layer 22, and the upper level of the low dielectricconstant film 46 which fills in between the wires of the second wiringlayer 22 is higher than the top level of the wires. Because of this, thecapacitance between the wires of the second wiring layer 22 is reducedmore compared with the structure disclosed in connection with the secondembodiment.

After this, a passivation layer and bonding pads are formed, and thewafer manufacturing process for the semiconductor integrated circuit iscompleted.

In this embodiment, a silicon oxide film is formed on the top of thewires, in order to make the top level of the low dielectric constantfilm 28 which fills in between the wires higher than the top level ofthe wires. However, the invention is not limited to this structure. Forexample, the capacitance between the wiring layers 18 and 22 can befurther reduced by forming a fluorinated silicon oxide film, which has alower dielectric constant than the silicon oxide film, on the top of thewires. Moreover, it is also possible to use other materials having aneven lower dielectric constant to form the film on the top of the wires.Furthermore, in this present embodiment, the resist pattern is removedafter the patterning of the silicon oxide film on the wiring. However,it is also possible to remove the resist pattern after forming thewires, or after performing the etching of the surface portions of theunderlying dielectric layer.

At least in this embodiment, it is possible to etch-back the underlyingfilm 26 so that portions of the underlying film on the surface of theunderlying dielectric layer 12 between the wires and on the siliconoxide film 42 on the top of the wires are removed before forming the lowdielectric constant film 28. As a result, the lower level of the lowdielectric constant film can be made lower than the upper level of thewires by the distance of d1.

FIGS. 10A, 10B and 10C and FIG. 11D are cross-sectional views showingthe formation processes of a wiring structure according to the fourthembodiment of the invention.

As shown in the FIG. 10A, and as also shown in connection with thesecond embodiment, surface portions of an underlying dielectric layer 12between wires of a first wiring layer 18 are etched to a depth of d1after the underlying dielectric layer 12 and the first wiring layer 18,which includes wires 18 a, 18 b and 18 c, are formed over asemiconductor substrate 10. Next, a fluorinated silicon oxide film isdeposited by using high density plasma CVD to form an underlying film26.

Next, as shown in FIG. 10B, a low dielectric constant film 28 formed offluorinated polyimide is formed by applying a coating solution whichcontains fluorinated polyimide precursors, and curing.

Next, as shown in FIG. 10C, the surface of the low dielectric constantfilm 28 is planarized by CMP. In this embodiment, unlike the secondembodiment, the CMP is terminated at a point at which the surface isplanarized, instead of continuing the CMP until all the low dielectricconstant film 28 above the wires of the first wiring layer 18 isremoved. The film thickness of the low dielectric constant film 28 abovethe wiring at this point is t3. Finally, a fluorinated silicon oxidefilm is deposited, by high density plasma CVD, and a cap film 30 isformed. By the above-mentioned process, the interlayer dielectric layer50, including the underlying film 26, the low dielectric constant film28 which fills in spaces between the wires of the first wiring layer 18and has a specific thickness over the top of the wires, and the cap film30 are formed. Unlike the second embodiment, the low dielectric constantfilm 28 is formed not only between the wires but also above the wires.Because of this, the capacitance between the wires and between thewiring layers is further reduced compared to the structure disclosed inconnection with the second embodiment.

When the thickness t3 of the low dielectric constant film 28 above thewiring after the CMP is not sufficient, it is possible to increase thethickness of the cap film 30. It is also possible to form another lowdielectric constant film on the low dielectric constant film 28.

In this embodiment, unlike the second embodiment, since the underlyingfilm 26 on the wires of the first wiring layer 18 is not used as anetching stopper when performing the CMP of the low dielectric constantfilm 28, it is necessary to perform the CMP with a high degree ofcontrollability and uniformity. It is possible to improve the degree ofcontrollability of the CMP through the selection of a forming method ofthe low dielectric constant film 28. For example, a low dielectricconstant film 28 of amorphous fluorinated carbon can be deposited by ahigh density plasma CVD method in which a substrate bias is applied suchthat the surface of the deposited film is virtually flat except for theprotrusions on wide wires. In this case, as disclosed in the U.S. Pat.No. 5,036,015, it is possible to detect a point at which the protrusionson wide wires are removed and the entire surface of the low dielectricconstant film 28 becomes flat by the change of the motor current of theCMP apparatus. Moreover, as disclosed in J. M. Neirynck et al.,Materials Research Society Symposium Proceedings, Vol. 381 (1995) P.229, CMP characteristics of a low dielectric constant film can beadjusted by the curing condition. Depending on the kind of the materialof the low dielectric constant film, CMP is performed after performingheat processing for removing the solvents i.e., at a temperature ofabout 150° C. or less, after performing a heat processing for performinga partial curing i.e., at a temperature of about 200-300° C., or afterperforming a complete curing i.e., at a temperature of about 350-450° C.

Next, via holes are formed in the interlayer dielectric layer 50 andplugs are formed (not shown). At this time, the cap film 30 can be usedas a mask for forming the via holes in the low dielectric constant film28. That is, a resist pattern corresponding to the via holes is formedon the cap film 30, and after apertures corresponding to the via holesin the cap film 30 are formed, the via holes are formed in the lowdielectric constant film 28 by anisotropic plasma etching using anoxygen-based gas atmosphere. By using this method, it is possible toform via holes in the low dielectric constant film 28 made of a materialwhich has poor ashing resistance. Many of the organic materials that arecategorized as low dielectric constant materials, as described in theabove-mentioned category 3, have poor ashing resistance. Moreover,organic porous materials or the like have poor ashing resistance.

For the anisotropic etching of the low dielectric constant film, aparallel-plate RIE apparatus, an ICP plasma etching apparatus, an ECRplasma etching apparatus, a helicon plasma etching apparatus or the likecan be appropriately used. These apparatuses, except for theparallel-plate RIE apparatus, should employ a substrate bias toaccelerate oxygen ions perpendicular to the substrate with anappropriate energy. An etching atmosphere including oxygen can be used.Other gasses such as N₂O, H₂O, CO or the like can be added. In order toensure the anisotropic etching, the substrate temperature during etchingis preferably kept low i.e., about 100° C. or less; preferably, about50° C. or less; even more preferably, about 20° C. or less; and mostpreferably, about 0° C. or less. Moreover, in order to increase thedirectionality of the ions, thereby ensuring proper anisotropic etching,the pressure of the etching atmosphere is preferably kept low i.e.,about 100 mtorr or less; preferably, about 20 mtorr or less; even morepreferably, about 10 mtorr or less; and most preferably, about 5 mtorror less. In order to obtain an acceptable etching speed under these lowtemperature and low pressure conditions, it is preferable to use highdensity plasma etching such as ICP, ECR, helicon plasma etching or thelike. Depending on the material of the low dielectric constant film 28,adding fluorine-based gas such as CF₄, C₂F₆, C₄F₈ or the like can makethe etching speed higher.

The resist pattern can be removed after the apertures corresponding tothe via holes are formed in the cap film 30, and the low dielectricconstant film can be etched using the cap film as the mask.Alternatively, since the resist is also etched by anisotropic plasmaetching using an oxygen-based gas atmosphere, it is possible to removethe resist pattern simultaneously when forming the via holes in the lowdielectric constant film 28 without performing a separate resist removalprocess. In this case, it is preferable to set the etching conditions sothat the resist pattern removal is completed before the completion ofthe via hole etching.

For the purpose of being used as a mask, the material for the cap filmis not limited to fluorinated silicon oxide. Various types of inorganicmaterials can be used as the cap film. For example, silicon oxide,silicon nitride, silicon oxynitride or the like can be used. Moreover,the deposition method for the cap film is not limited to the highdensity plasma CVD. For example, conventional plasma CVD, SOG or thelike can be used. However, in order to decrease the wiring capacitance,it is preferable to use a fluorinated silicon oxide film which has a lowdielectric constant.

It is possible to remove the resist by ashing, and then the via holesare formed in the low dielectric constant film 28 by an anisotropicetching using an oxygen-based gas atmosphere. However, adjustment of theashing conditions is necessary since low dielectric constant materialshaving poor ashing resistance tend to be etched isotropically by theashing. It is also possible to remove the resist pattern by using asolvent which dissolves the resist but does not dissolve the lowdielectric constant film 28.

On the other hand, methylsiloxane SOG, hydrogen silsesquioxane SOG,inorganic porous materials and the like have relatively high ashingresistances. When these materials are used for the low dielectricconstant film 28, it is possible to form the via holes by anisotropicplasma etching using an fluorine-based gas atmosphere, using a resistmask. However, even when these kind of materials are used, the surfacesof the low dielectric constant film, which are exposed on the side wallsof the via holes, may deteriorate by the ashing process to remove theresist pattern. For example, the side walls of the low dielectricconstant film may become hygroscopic. Because of this, it is necessaryto adjust the ashing conditions. Alternatively, as disclosed in Ito etal., Journal of the Electrochemical Society, Vol. 137 (1990) p. 1212, itis preferable to perform a stabilizing process which uses a plasma thatcontains directional oxygen ions at low temperatures i.e., about 100° C.or below; preferably about 50° C. or below; more preferably about 20° C.or below and low pressures i.e., about 100 mtorr or below; preferablyabout 20 mtorr or below; more preferably about 10 mtorr or below. Afterthe stabilizing process, it is possible to perform ashing to remove theresist pattern. Alternatively, the stabilizing plasma treatment can becontinued until the resist pattern is removed. Moreover, it is alsopossible to omit the plasma ashing process, or to shorten the ashingtime, by using a solvent to remove the resist pattern.

The same process is repeated as necessary, and the second and followingwiring layers and the second and following interlayer dielectric layersare formed. FIG. 11D shows a cross sectional view in which a secondwiring layer 22, which contains wires 22 a, 22 b and 22 c, and a secondinterlayer dielectric layer 52 comprising an underlying film 34, a lowdielectric constant film 36 which is formed between and on top of thewires of the second wiring layer 22, and a cap film 38, are formed.

The cap film 30 also functions as an adhesion film for the second wiringlayer 22 with respect to the interlayer dielectric layer 50. Moreover,the cap film 30 functions to prevent diffusion of the water from the lowdielectric constant film 28 to the second wiring layer 22. Fluorinatedsilicon oxide film which is deposited by high density plasma CVD has ahigh water diffusion prevention effect, and since the film thicknessneeded to obtain necessary diffusion prevention effect is small, thefilm thickness of the cap film 30 can be decreased. As a result, thecapacitance between the wires of the second wiring layer 22 and betweenthe first and the second wiring layer can be reduced. Specifically, thefilm thickness of fluorinated silicon oxide film which is deposited byhigh density plasma CVD can be made as thin as about 25 nm or less, orit can be as thin as 10 nm, depending on the conditions. Of course, whenthere are no adhesion and water diffusion problems, and the lowdielectric constant film 28 is formed using a material with which thevia holes can be formed using a resist mask, it is possible to omit thecap film 30. Moreover, it is possible to use a silicon oxide film, asilicon nitride film, a silicon oxynitride film or the like, as the capfilm 30 in order to improve adhesion and to prevent water diffusion.

After this, a passivation layer and bonding pads are formed, and thewafer manufacturing process of the semiconductor integrated circuit iscompleted.

FIGS. 12A, 12B, 12C and FIG. 13D are cross sectional views showing theformation processes for a wiring structure according to the fifthembodiment of the invention.

As shown in FIG. 12A, a first wiring layer 18 which includes wires 18 a,18 b and 18 c is formed, and a interlayer dielectric layer 50, whichcomprises an underlying film 26, a low dielectric constant film 28,which is formed between and on top of the wires of the first wiringlayer 18, and a cap film 30 are formed, similar to the process describedin connection with the fourth embodiment. Here, the film thickness ofthe cap film 30 is t6.

Next, as shown in FIG. 12B, via holes are formed in the interlayerdielectric layer 50, and plugs are formed (not shown in the Figure).Next, a metal film for forming the second wiring layer is formed on thecap film 30. A resist pattern 54 is formed on this metal film, and thesecond wiring layer 22, which includes wires 22 a, 22 b and 22 c, isformed by an anisotropic plasma etching in which a chlorine-based gasatmosphere is used. Here, the space between the wires of the secondwiring layer 22 is s11. This etching is completed without removing thecap film 30 between the wires of the second wiring layer 22.

Next, as shown in FIG. 12C, after removing the resist pattern 54, andafter removing the cap film 30 between the wires of the second wiringlayer by an anisotropic etching which uses a fluorine-based gasatmosphere, surface portions of the low dielectric constant film 28between the wires of the second wiring layer 22 are etched to athickness of d11 by an anisotropic plasma etching which uses anoxygen-based gas atmosphere.

Next, as shown in FIG. 13D, a second interlayer dielectric layer 56,including an underlying film 34, a low dielectric constant film 36,which is formed between and on top of the wires of the second wiringlayer 22, and a cap film 38, is formed by repeating the same formationprocess. Here, the thickness of the underlying film 34 of the secondinterlayer dielectric layer 22 between the wires of the second wiringlayer is t11, and the thickness of the underlying film 34 on the top ofthe wires of the second wiring layer is t12.

In the wiring structure of this embodiment, unlike the fourthembodiment, portions of the cap film 30 of the first interlayerdielectric layer 50 are removed, and surface portions of the lowdielectric constant film between the wires of the second wiring layer 22are etched to the depth of d11. Because of this, the bottom level of thelow dielectric constant film 36 of the second interlayer dielectriclayer 56 is lower than the bottom level of the wires of the secondwiring layer 22. Accordingly, since the electric field between the wiresof the second wiring layer 22 is effectively confined within the lowdielectric constant film 36, the capacitance between the wires of thesecond wiring layer 22 is further reduced compared to the structuredisclosed in connection with the fourth embodiment. It is preferable tomake the value of (d11+t6−t11) to be about 20% or more, and morepreferably, about 50% or more of the space s11 between the wires of thesecond wiring layer, in order to effectively reduce the capacitancebetween the wires of the second wiring layer 22.

Then, the third and following wiring layers and interlayer dielectriclayers are formed as needed, and a passivation layer and bonding padsare formed, and the wafer process is completed.

In this embodiment, after the wires of the second wiring layer 22 areformed by anisotropic plasma etching, which uses a chlorine-based gasatmosphere, and the resist is removed, portions of the cap film 30between the wiring of the second wiring layer 22 are removed by ananisotropic plasma etching which uses a fluorine-based gas atmosphere.Further, the surface portions of the low dielectric constant film 28 areetched by anisotropic plasma etching, which uses an oxygen-based gasatmosphere. However, the invention is not limited to this. For example,depending on the material of the low dielectric constant film 28, it ispossible to etch the surface portions of the low dielectric constantfilm 28 using anisotropic plasma etching using a fluorine-based gasatmosphere.

In this embodiment, both the cap film 30 and the surface portions of thelow dielectric constant film 28 between the wires of the second wiringlayer 22 are etched. However, the capacitance between the wires of thesecond wiring layer 22 can be reduced compared to the structuredisclosed in connection with the fourth embodiment by simply removingthe cap film 30 between the wires of the second wiring layer 22.

In the first to fourth embodiments described above, both the firstwiring layer 18 and the second wiring layer 22 are formed by an etchingmethod, but the invention is not limited to this method. For example, itis possible to form the second wiring layer 22 by the damascene method.

FIGS. 14A, 14B, 14C, FIGS. 13D, 13E, 13F and FIG. 14G arecross-sectional views which show the formation processes of a wiringstructure according to a sixth embodiment of the invention.

First, as shown in FIG. 14A, a first wiring layer 18, including wires 18a, 18 b, 18 c, an interlayer dielectric layer 32, including anunderlying film 26, a low dielectric constant film 28, which fills inthe spaces between the wires of the first wiring layers, and a cap film30 are formed by the same processes as described in connection with thesecond embodiment.

Next, as shown in FIG. 14B, a resist pattern 58 which corresponds to thevia holes and which connects wires of the first wiring layer 18 andwires of the second wiring layer are formed in the interlayer dielectriclayer 32. An anisotropic plasma etching, which uses a fluorine-based gasatmosphere, is performed using this resist pattern 58 as a mask, and viaholes 60 are formed in the interlayer dielectric layer 32. Thedimensions of the via holes 60 are set such that the low dielectric film28 of the interlayer dielectric layer 32 is not exposed on side walls ofthe via holes. In particular, when a low dielectric constant materialwhich has poor ashing resistance is used as the material for the lowdielectric constant film 28, it is preferable to set the relationshipbetween the dimensions of the wires of the first wiring layer 18 and thedimensions of the via holes 60 to be such that the low dielectricconstant material is not exposed on the side walls of the via holes 60even if, for example, mask misalignment occurs during thephotolithography process.

As shown in FIG. 14C, after the resist pattern 58 is removed, a lowdielectric constant film 62, which is made of, for example, afluorinated polyimide, is formed by coating and curing a solution whichcontains fluorinated polyimide precursors on the first interlayerdielectric layer 50. At this time, via holes 60 are also filled in bythe fluorinated polyimide. Since the surface of the interlayerdielectric layer 50 is flattened, the surface of the low dielectricconstant film 62 also becomes virtually flat when the film thickness ofthe low dielectric constant film 62 is thicker than the dimension of thevia holes 60. It is possible to further increase the flatness byperforming CMP after the coating and curing. Here, the low dielectricconstant film 62 is formed using a low dielectric constant materialwhich has poor ashing resistance. Furthermore, a fluorinated siliconoxide film, for example, is deposited on the low dielectric constantfilm 62, forming a cap film 64. This low dielectric constant film 62 andcap film 64 form a intra-layer dielectric layer 66 between wires of thesecond wiring layer.

Next, as shown in FIG. 15D, resist pattern 68, corresponding to groovesin which wires of the second wiring layer are to be formed, is formed onthe cap film 64, and apertures are formed in the cap film 64 byanisotropic plasma etching, which uses a fluorine-based gas atmosphere.

Next, as shown in FIG. 15E, grooves 70 are formed in the low dielectricconstant film 62 by an anisotropic etching, which uses an oxygen-basedgas atmosphere. At that time, the over-etching amount is set so that thelow dielectric constant film 62 within the via holes 60 is removed. Asdescribed in connection with the fourth embodiment, whereby via holesare formed in the low dielectric constant film 28, it is possible toremove the resist pattern 68 in advance, or to simultaneously remove theresist pattern 68 during the etching of the low dielectric constant film62.

Next, as shown in FIG. 15F, a metal film 72 is formed over the entiresubstrate surface in order to form plugs which connect wires of thefirst wiring layer 18 with wires of the second wiring layer, and to formwires of the second wiring layer. For example, a titanium film which hasa thickness of about 10-100 μm, a titanium nitride film which has athickness of about 20-200 μm, and a copper film which has a thickness ofabout 0.5-2 μm are formed in the order. For the deposition of thetitanium film and titanium nitride film, for example, an ionizedsputtering method (G. Dixit et al., International Electron DevicesMeeting Digest of Technical Papers (1996) p. 357) is used, and for thedeposition of the copper film, a CVD method is used. At this time,deposition conditions with high coverage are selected so that the viaholes 60 and the grooves 70 are filled.

As shown in FIG. 16G, the metal film 72, which is formed on the cap film64 is removed, for example, by a CMP method. By so doing, the plugs 74embedded within the via holes 60, which connect the wires of the firstwiring layer 18 with the wires of the second wiring layer, and the wiresof the second wiring layer 22 which are embedded within the grooves 70are formed. Furthermore, as needed, an oxidation prevention film isformed on the surface of the wires of the second wiring layer 22, asdisclosed in, for example, K. Ueno et al., Symposium on VLSI TechnologyDigest of Technical Papers (1995) p. 27.

In this embodiment, a copper-based wiring formed mainly of a copper filmis formed as the wires of the second wiring layer 22. In thisembodiment, pure copper film is used, but it is also possible to usevarious copper-containing films such as Cu—Ti, Cu—Zr or the like.Meanwhile, the titanium film functions to improve the adhesion of thesecond wiring layer 22 and reduce the contact resistance between thewire of the first wiring layer 18 and the wire of the second wiringlayer 22. The titanium nitride film has a function of preventingdiffusion of copper. Furthermore, instead of a titanium film, variousfilms of refractory metals such as zirconium, hafnium, tantalum,tungsten or the like can be used. Also, if there is no problem ofadhesion or contact resistance, it is possible to omit this film.Instead of a titanium nitride film, various films of refractory metalcompounds, such as zirconium nitride, hafnium nitride, tantalum nitride,tungsten nitride, TiSiN, TaSiN, WSiN, or the like can be used. Theserefractory metal compounds are not limited to substances withstoichiometric ratios. Among the refractory metals, at least Ta, W, orthe like can be used in a monolayer film to improve adhesion and toprevent the diffusion of copper.

After that, the third and subsequent wiring layers are formed as needed,and a passivation layer and bonding pads are formed, and the wafermanufacturing process for the semiconductor integrated circuit iscompleted.

In this embodiment, when forming the grooves 70, apertures are formed inthe cap film 64 by anisotropic plasma etching, which uses afluorine-based gas atmosphere. After that, etching is performed on thelow dielectric constant film 62 by an anisotropic plasma etching whichuses an oxygen-based gas atmosphere. In the anisotropic plasma etchingprocess, which uses an oxygen-based gas atmosphere, the etching speed ofthe fluorinated silicon oxide film is very slow so the cap film 30includes a fluorinated silicon oxide film which is exposed at the bottomof the groove 70 and is barely etched. Therefore, the depth of thegrooves 70 is automatically determined by the film thickness of the lowdielectric constant film 62. Furthermore, as shown in FIG. 1SE, eventhough the mask of the grooves 70 is made to be larger than the mask ofthe via holes 60, the via holes 60 are not enlarged when the grooves 70are formed. Furthermore, as shown in FIG. 17, even if the mask ofgrooves 70 is shifted with respect to the via holes 60, the dimensionsof the via holes 60 are not enlarged. Thus, the method according to thisembodiment has an advantage in that the tolerance for mask misalignmentis large.

In this embodiment, the metal film 72 is formed and CMP is performedafter the via hole 60 and the groove 70 are formed. Therefore, the plugs74 and wires of the second wiring layer 22 are simultaneously formed.However, the invention is not limited to this structure. It is alsopossible to form the metal film and to perform CMP to form plugs 74 inthe via holes 60, and to thereafter form the grooves 70 and wires of thesecond wiring layer 22.

In this embodiment, the cap film 64 is left as part of the intra-layerdielectric layer 66 between the wires of the second wiring layer 22, butthe invention is not limited to this structure. For example, by properlysetting the conditions of the CMP, it is possible to remove the cap film64 during the CMP to form the wires of the second wiring layer 22.

In the first interlayer dielectric layer 32 of the structure shown inFIGS. 14A-14C, FIGS. 15D-15F, and FIG. 16G, the low dielectric constantfilm 28 is formed only in the sections to fill in the spaces between thewires of the first wiring layer 18, and the second wiring layer 22 isformed with the damascene method. Meanwhile, it is also possible to formthe wires of the second wiring layer 22 by the damascene process whenthe low dielectric constant film is formed not only between the wiresbut also on the top of the wires of the first wiring layer 18.

FIGS. 18A, 18B, and 18C, FIGS. 19D, 19E, and 19F, FIGS. 20G, 20H, and20I, and FIG. 21J are cross-sectional views showing the formationprocesses of a wiring structure according to the seventh embodiment ofthe invention.

As shown in FIG. 18A, and as described in connection with the fourthembodiment, a first wiring layer 18 is formed, and a first interlayerdielectric layer 50, including an underlying film 26, a low dielectricconstant film 28, which is formed between and on the wires of the firstwiring layer 18, and a cap film 30, are formed. The surface of the lowdielectric constant film 28 is planarized. The low dielectric constantfilm 28 is formed by a material which has poor ashing resistance.

Next, as shown in FIG. 18B, a resist pattern 58 corresponding to viaholes is formed and the cap film 30 is removed at portions correspondingto the via holes by anisotropic plasma etching using a fluorine-basedgas atmosphere. Then, as shown in FIG. 18C, the via holes 60 are formedin the low dielectric constant film 28 by anisotropic plasma etchingusing an oxygen-based gas atmosphere. At this time, the cap film 30functions as a mask.

Next, as shown in FIG. 19D, in order to form an intra-layer dielectriclayer 66 which insulates between wires of the second wiring layer, a lowdielectric constant film 62 and a cap film 64 are formed, in order, overthe entire surface of the substrate. For the formation of the lowdielectric constant film 62, for example, a coating method is used. Thelow dielectric constant film 62 is also formed within the via holes 60.Since the surface of the first interlayer dielectric layer 50 is flat,the surface of the low dielectric constant film 62 is also virtuallyflat.

Then, as shown in FIG. 19E, a resist pattern 68 is formed whichcorresponds to grooves within which wires of the second wiring layer areformed, and etching of the cap film 64 is performed by an anisotropicplasma etching.

As shown in FIG. 19F, grooves 70 are formed in the low dielectricconstant film 62 by anisotropic etching using an oxygen-based gasatmosphere. At this time, the over-etching time is set so that the lowdielectric constant film 62, which is formed within the via holes 60, isfully removed. At this time, the cap film 30 of the first interlayerdielectric layer 50 is exposed at the bottom of the grooves 70. Thefluorinated silicon oxide film which forms the cap film 30 ispractically not etched by the anisotropic plasma etching process for thelow dielectric constant film 62. Therefore, it is possible to accuratelycontrol the depth of the groove 70. Furthermore, since the cap film 30functions as a mask, enlargement of the via holes during the formationof the grooves 70 is prevented. Next, anisotropic plasma etching usingan fluorine-based gas atmosphere is performed and the underlying film 26of the first interlayer dielectric layer 50, which is exposed at thebottom of the via holes 60 is removed. As a result, upper surfaces ofthe wires of the first wiring layer 18 are exposed at the bottom of thevia holes 60. At this time, the cap film 30 of the first interlayerdielectric layer 50 and the cap film 64 of the intra-layer dielectriclayer 66 are simultaneously etched. FIG. 19F shows an example in whichthe cap film 30 and 64 remain.

Next, as shown in FIG. 20G, plugs 74 and wires of the second wiringlayer 22 are formed within the via holes 60 and the grooves 70 by thedamascene method.

After this, a third and subsequent wiring layers are formed as needed.FIGS. 20H, and 20I and FIG. 21J are examples of formation processes forforming the third wiring layer by the damascene method.

First, as shown in FIG. 20H, in order to form the second interlayerdielectric layer 76, which insulates between the second wiring layer 22and the third wiring layer, an underlying film 78, a low dielectricconstant film 80, and a cap film 82, are formed in order. Then, by thesame method as described in connection with the formation of via holes60 for connecting the wires of the first wiring layer 18 with the wiresof the second wiring layer 22, via holes 84 for connecting the wires ofthe second wiring layer 22 with the wires of the third wiring layer areformed.

Next, as shown in FIG. 20I, in order to form a third intra-layerdielectric layer 86 between wires of the third wiring layer, a lowdielectric constant film 88 and a cap film 90 are formed in order. Atthis time, the low dielectric constant film 88 is also formed within thevia holes 84. Then, utilizing the same method as for the formation ofthe grooves 70 in the second intra-layer dielectric layer, grooves 92are formed within the third intra-layer dielectric layer. At this time,the underlying film 78 of the second interlayer dielectric layer 76,which is exposed at the bottom of the via hole 84 is removed. ThisFigure shows an example in which the cap film 82 of the secondinterlayer dielectric layer 76 at the bottom of the groove 92 and thecap film 90 of the third intra-layer dielectric layer 86 between thewires of the third wiring layer remain.

As shown in FIG. 21J, plugs 94, which connect wires of the second wiringlayer 22 with wires of the third wiring layer 96 are formed within thevia holes 84, and wires of the third wiring layer 96 are formed in thegrooves 92 by the damascene method.

After that, the forth and subsequent wiring layers are formed as needed,a passivation layer and bonding pads are formed and the wafermanufacturing process of the semiconductor integrated circuit iscompleted.

In this embodiment, films of materials which have poor ashing resistanceare used for the low dielectric constant films 28, 62, 80, and 88, andvia holes 60 and 84 and grooves 70 and 92 are formed by anisotropicetching using an oxygen-based gas atmosphere, using cap films 30, 64,82, and 90 as masks. However, the invention is not limited to this. Itis also possible to form the low dielectric constant films 28, 62, 80,and 88 from materials resistant to the ashing, e.g. siloxane SOG and toform the via holes 60 and 84 and the grooves 70 and 92 by an anisotropicplasma etching using a fluorine-based gas atmosphere with resist masks.In this case, it is possible to omit the cap films 30, 64, 82, and 90.

In this embodiment, the via holes 60 and 84 and grooves 70 and 92 areformed using anisotropic etching using an oxygen-based gas atmosphere.In the anisotropic etching using an oxygen-based gas atmosphere, theresist is also etched. Therefore, separate resist removal procedures canbe omitted by simultaneously removing the resist pattern during theetching process for the formation of the via holes 60 and 84 and thegrooves 70 and 92. For this purpose, it is preferable to set filmthickness of the low dielectric constant films 28, 62, 80, and 88 andthe resist and the plasma etching conditions to be such that, upon thecompletion of the etching of the low dielectric constant films 28, 62,80, and 88, the removal of resist is already finished. Even if theremoval of the resist pattern is completed first, the dimensionalaccuracy of the via holes 60 and 84 and grooves 70 and 92 does notdeteriorate because the cap films 30, 64, 82 and 92 exist on the lowdielectric constant films 28, 62, 80, and 88 and function as masks.

In this embodiment, when via holes 60 and 84 and grooves 70 and 92 areformed, the surface of the substrate is flat. Therefore, even if thefilm thickness of the resist for forming resist patterns 58, 68, and thelike are thin, the resist can be uniformly coated. By making the resistfilm thin, the process of simultaneously performing resist removal andetching of the via holes 60 and 84 and the grooves 70 and 92 becomeseasier as described above. Further, it is possible to improve theresolution by decreasing the resist thickness. For example, it is easyto make the resist film thickness as thin as about 0.5 μm or less, andit is even possible to make them as thin as about 0.3 μm or less. Inorder for the removal of the resist to be finished upon the completionof etching of the low dielectric constant film, the film thickness ofresist should be equal to or less than the film thickness of the lowdielectric constant film to be etched. That is, in the case of theformation of the via holes 60 and 84, the resist film thickness shouldbe equal to or less than the depth of the via holes, and in the case ofthe formation of the grooves 70 and 92 the resist film thickness shouldbe equal to or less than the total of the depths of the grooves and viaholes. Preferably, the resist film thickness should be about 70% orless; more preferably about 50% or less; most preferably about 30% orless of the depth of the via holes or the total of the depths of thegrooves and via holes.

In this embodiment, the via holes 60 are formed in the low dielectricconstant film with the underlying film 26 of the first interlayerdielectric layer 50 remaining. After that, when the grooves 70 areformed in the second intra-layer dielectric layer 66, the underlyingfilm 26 at the bottom of the via holes 60 is removed. However, it isalso possible to remove the underlying film 26 at the bottom of the viaholes 60 by anisotropic etching using an fluorine-based gas atmosphereafter the formation of the via holes 60 in the first interlayerdielectric layer.

Also, in this embodiment, the cap film 64 remains on the surface of thesecond intra-layer dielectric layer 66, but the invention is not limitedto this structure. For example, it is possible to remove the cap film 64when removing the underlying film 26 exposed at the bottom of the viaholes 60. By removing the cap film 64 between the wires of the secondwiring layer 22, the capacitance between the wires of the second wiringlayer 22 is further reduced. In this case, it is required toappropriately set the CMP conditions to form the second wiring layer 22,so that the surface of the low dielectric constant film 62 is notdamaged. In this embodiment, the cap film 64 of the second intra-layerdielectric layer 66 remains when the second wiring layer 22 is formed.However, it is also possible to remove the cap film 64 by changing thecondition of the CMP used for forming the second wiring layer 22. Atleast in this case, it is possible to form the cap film 64 by a materialwith a low CMP speed, such as silicon nitride or the like. The cap film64 which includes a material of this type can be used as an etching stopfor the CMP. By using the etching stop film, even when the over-etchingamount becomes large due to the fluctuation of the process conditions,it is possible to prevent damaging the surface of the low dielectricconstant film 62. Because silicon nitride has a higher dielectricconstant than silicon oxide, it is preferable to remove the siliconnitride film after it is used as the etching stop film to reduce thecapacitance between the wires.

In the embodiment shown in FIGS. 18 through 21, after via holes 60 areformed in the first interlayer dielectric layer 50, the intra-layerdielectric layer 66 is formed and the groove 70 is formed in theintra-layer dielectric layer 66. However, the invention is not limitedto this. For example, it is possible to form via holes 60 in the firstinterlayer dielectric layer 50 after grooves 70 are formed in theintra-layer dielectric layer 66.

FIGS. 22A, 22B, and 22C and FIGS. 23D and 23E are cross-sectional viewsshowing the formation processes of the wiring structure in this lattercase.

First, as shown in FIG. 22A, using the same processes of the previousembodiment, a first wiring layer 18, a first interlayer dielectric layer50 including an underlying film 26, a low dielectric constant film 28,which is formed between and on wires of the first wiring layer 18, and acap film 30 are formed. After that, a low dielectric constant film 62and a cap film 64, which form a second intra-layer dielectric layer 66that insulates between wires of the second wiring layer, are formed onthe first interlayer dielectric layer 50.

Next, as shown in FIG. 22B, a resist pattern corresponding to grooves inwhich wires of the second wiring layer will be formed is formed,apertures are formed in the cap film 64 by anisotropic plasma etchingusing a fluorine-based gas atmosphere, and grooves 70 are formed in thelow dielectric constant film 62 by an anisotropic plasma etching usingan oxygen-based gas atmosphere.

Then, as shown in FIG. 22C, a resist pattern 98 corresponding to the viaholes is formed and exposed portions of the cap film 30 of the firstinterlayer dielectric layer 50 are removed by an anisotropic plasmaetching using a fluorine-based gas atmosphere.

Next, as shown in FIG. 23D, the low dielectric constant film 28 isetched by anisotropic plasma etching using an oxygen-based gasatmosphere, and the via holes 60 are formed by removing the underlyingfilm 26 by performing an anisotropic plasma etching which uses afluorine-based gas atmosphere.

As shown in FIG. 23E, via plugs 74, for connecting the second wiringlayer 22 and the first wiring layer 18, and wires of the second wiringlayer 22 are formed by the damascene process.

After this, the third and subsequent wiring layers are formed as needed,the passivation layer and bonding pads are formed, and the wafermanufacturing process of the semiconductor integrated circuit iscompleted.

In the previously explained embodiments, the low dielectric constantfilm 28 of the first interlayer dielectric layer 50 is exposed on theside walls of the via holes 60 and the low dielectric constant film 62of the second intra-layer dielectric layer 66 is exposed on the sidewalls of the grooves 70. The metal film for forming the second wiringlayer 22 and the plugs 74 between the first and the second wiring layeris deposited in these via holes 60 and grooves 70. As a result, theplugs 74 contact the low dielectric constant film 28 exposed on the sidewalls of the via holes 60 and the wires of the second wiring layer 22contact the low dielectric constant film 62 exposed on the side walls ofthe grooves 70. Similarly, the plugs 94 between the second and thirdwiring layers contact the low dielectric constant film 80 of the secondinterlayer dielectric film on the side walls of the via holes 84 and thewires of the third wiring layer 96 contact the low dielectric constantfilm 88 of the third intra-layer dielectric-layer on the side walls ofthe grooves 92. Depending on the materials of the low dielectricconstant films and on the process conditions, however, the lowdielectric constant films may have a bad influence on the plugs andwires. For example, the low dielectric constant films may include asubstantial amount of water. In such cases, it is preferable to avoidthe direct contact of the plugs and wires with the low dielectricconstant films.

FIGS. 24A and 24B are cross-sectional views showing the formationprocesses of the wiring structure in which plugs and wires are notdirectly contact the low dielectric constant films.

First, following similar processes as described in connection with theprevious embodiments, a structure, such as shown in FIGS. 19F and 23D,having a first wiring layer 18, a first interlayer dielectric layer 50including an underlying film 26, a low dielectric constant film 28,which is formed between and on the wires of the first wiring layer 18;and a cap film 30, a second intra-layer dielectric layer 66 including alow dielectric constant film 62 and a cap film 64, via holes 60, formedin the first interlayer dielectric layer 50, and grooves 70 formed inthe second intra-layer dielectric layer 66 are formed. Next, as shown inFIG. 24A a cover film 71 of, for example, fluorinated silicon oxide isdeposited on the surface of the substrate including the side walls ofthe via holes 60 and the side walls of the grooves 70. The cover film isformed by, for example, high density plasma CVD with a substrate bias.

After that, the cover film 71 is etch-backed by using, for example, ananisotropic plasma etch using a fluorine-based gas atmosphere, such thatthe cover film is removed at portions on the bottoms of the via holes 60and the grooves 70. As a result, as shown in FIG. 24B, side wall films73 on the side wall of the grooves 70 and side wall films 75 on the sidewalls of the via holes 60 are formed. The side wall films 73 cover thelow dielectric constant film 62 exposed on the side walls of the grooves70, and the side wall films 75 cover the low dielectric constant film 28exposed on the side walls of the via holes 60.

Then, as shown in FIG. 24C, plugs 74 in the via holes 60 and wires ofthe second wiring layer 22 in the grooves 70 are formed by the damascenemethod. In this structure, since the side walls of the via holes 60 andthe grooves 70 are covered with the side wall films 75 and 73, the plugsand wires do not contact the low dielectric constant films 28 and 62.

The same process can be repeated to form the third and subsequent wiringlayers with side wall films formed on the side walls of the via holesand grooves.

In this embodiment, the side wall films are formed by depositing a coverfilm using high density plasma CVD with a substrate bias followed by ananisotropic etch-back. Therefore, even when the side walls of the viaholes 60 and the grooves 70 are formed substantially vertical,substantial portions of surfaces of the side wall films have uniformpositive slopes, except for portions around top edges of the via holesand grooves. In other words, the thickness of the side wall film onupper portions of the side walls is thinner than that on lower portionsof the side walls. The positive slope facilitates the filling of themetal films in the via holes 60 and the grooves 70 even when thedimensions of the via holes and grooves become small. The slope ispreferably about 2° or more, more preferably about 4° or more, or mostpreferably about 6° or more with respect to the normal of the mainsurface of the semiconductor substrate to sufficiently improve thefilling ability of the metal film. However, it is not preferable toincrease the slope too large, for example, more than about 8°, so that asufficient volume of the via hole or the groove remains to fill with themetal film.

The sloped side wall film is particularly effective to facilitate metaldeposition into the via holes and grooves when particular methods areutilized to deposit the metal film. For example, a thin and uniformdiffusion barrier layer of a titanium/titanium nitride bi-layer,titanium nitride, tantalum, tantalum nitride, tungsten nitride or thelike can be deposited by ionized sputtering on the sloped side wallfilms formed by high density plasma CVD with a substrate bias. This isbecause both high density plasma CVD and ionized sputtering utilize ionsaccelerated by substrate biases. Ionized sputtering can also bepreferably used to form a thin copper film on the diffusion barrierfilm. This copper film is used as a seed layer to deposit a thick copperfilm which fills the via holes and/or grooves by plating. The seed layeris also needed to form other low resistance metal films such as a goldfilm by plating.

Further, in this embodiment, side wall films are formed from a coverfilm deposited by high density plasma CVD. Silicon oxide deposited byhigh density plasma CVD has the ability to suppress water diffusionbetter than a film deposited by, for example, conventional plasma CVD.As described previously, the addition of fluorine to the film furtherimprove the ability to suppress water diffusion, as long as the fluorinecontent is limited to the range that a substantial amount of Si(—F)₂bonds are not included. Therefore, it is possible to decrease thethickness of the side wall film while keeping the ability to suppressthe water diffusion from the low dielectric constant film. Thus, it ispossible to improve the filling ability of the metal film in the viaholes 60 and the grooves 70 with small dimensions. For example, theminimum thickness of the side wall film around the top level of the lowdielectric constant film 28 can be reduced to about 15 nm or less. Insome cases, it can be reduced to about 10 nm or less. Even other cases,it can be reduce to about 5 nm or less.

Furthermore, in this embodiment, the side wall films are formed with afluorinated silicon oxide film which has a lower dielectric constantthan silicon oxide. Therefore, the capacitance between the wires can befurther reduced compare to the case that the side wall films are madewith a material having a higher dielectric constant, such as siliconoxide, silicon nitride, and the like.

In this embodiment, the side wall films are simultaneously formed bothon the side walls of the via holes 60 and the grooves 70. That is, thecover film is deposited after the via holes and grooves are formed andthe anisotropic etch-back is performed to form the side wall films onthe side walls of the via holes and grooves. However, the side wallsfilms for the via holes and the grooves can be formed in separateprocesses. Further, it is not always necessary to form side wall filmsboth on the side walls of the via holes and the grooves.

In this embodiment, a cover film 71 is formed by depositing afluorinated silicon oxide film by high density plasma CVD with asubstrate bias, and side wall films 75 and 73 are formed by an etch-backof the cover film 71. The following three advantages can be obtained:

1) Side wall films with positively sloped surfaces can be formed,thereby, improving the filling ability of the metal film in the viaholes and the grooves.

2) The thickness of the side wall film can be reduced while maintainingthe ability to suppress water diffusion thereby improving the fillingability of the metal film in the via holes and the grooves.

3) Side wall films with a low dielectric constant can be formed,thereby, reducing the capacitance between the wires.

However, to obtain the first two advantages, films of various othermaterials can be used. For example, a silicon oxide, a silicon nitrideor a silicon oxynitride film can be used to form the cover film 71.These films can be preferably deposited by a high density plasma CVDwith a substrate bias.

In the previously explained embodiments, for the first wiring layer 18,an aluminum-based wiring formed by an etching method is used. For thesecond wiring layer 22, a copper-based wiring formed by the damascenemethod is used. However, the invention is not limited to these methods.

In conventional semiconductor integrated circuits, aluminum-based wiringformed by an etching method is usually used. It is possible to form analuminum-based wiring by the damascene process, but the introduction ofnew equipment, such as a CMP apparatus and the like, is needed so it isgenerally preferable to use conventional etching methods to form analuminum-based wiring. Meanwhile, it is difficult to form copper-basedwiring by etching methods, so it is preferable to form it by thedamascene method. The damascene method can be also preferably used toform other low resistance material wiring such as a gold- andsilver-based wiring. It can be also used to form a tungsten-basedwiring.

In the wiring structure according to the invention, it is possible toprovide either an aluminum-based wiring layer or a copper-based wiringlayer, or plural layers of both wiring. It is also possible to provideother wiring, e.g. a tungsten-based wiring. The tungsten-based wiringcan be formed in small dimensions, although the resistance is relativelyhigh. The tungsten-based wiring can preferably be used for bit linewiring in a DRAM cell array, local wiring in a SRAM cell array, and thelike (e.g. T. Ueda et al., Symposium on VLSI Technology Digest ofTechnical Papers (1996) p. 142, K. Furumochi et al., International SolidState Circuits Conference Digest of Technical Papers (1996) p. 156).Aluminum-based wiring is widely used in conventional semiconductorintegrated circuits and can be formed at low cost. Since it has a lowerresistance than tungsten-based wiring, aluminum-based wiring isgenerally used for signal wiring, power wiring, and the like.Copper-based wiring has lower a resistance than that of thealuminum-based wiring, so it is possible to improve the operationalspeed of a semiconductor integrated circuit if, for example, it is usedfor long distance signal wiring, for example, wiring with a length ofmore than about 1 mm. It is also possible to improve the operationalspeed by reducing discrepancies in the operation timing in thesemiconductor integrated circuit chip due to the delay of a clock signalif a copper-based wiring is used for the wiring for clock signaldistribution. It is also possible to improve operation stability byimproving the power supplying capability if it is used for the power buswiring. Further, because the copper-based wiring has a higherelectromigration tolerance, the dimension of the wires can be reducedwithout degrading the reliability, if it is used for wires to carrylarge currents. As a result, the chip size of the integrated circuit canbe reduced.

As described above, by using copper-based wiring, it is possible toimprove the performance of the semiconductor integrated circuit.However, copper-based wiring technology has not yet matured into massproduction. Various problems remain to be solved in terms of theinfluence on transistor characteristics, productivity, cost, yield, andthe like. Although these problems may be solved technically, it isnecessary to develop apparatuses for implementing the copper filmforming process and the damascene process in order to facilitate massproduction. In particular, since Cu has the possibility of degradingtransistor characteristics, apparatuses for copper-based wiringprocesses should be carefully arranged in a clean room in order tominimize the risk of contaminating sensitive processes, for example,gate processes, by copper. Therefore, it is difficult to produce largeamounts of LSI's having a copper-based wiring by renovating an existingproduction factory. Furthermore, in the case that a new factory isconstructed, since the copper-based wiring processes have not yet fullymatured, the cost for the apparatus and process development becomeshigh. Moreover, the material cost is also high compared to utilizationof aluminum-based wiring.

Due to the reasons described above, at least at present, copper-basedwiring has a disadvantage in terms of the cost compared toaluminum-based wiring. Accordingly, although there is a demand forsemiconductor integrated circuits with high performance usingcopper-based wiring, there is an even larger demand for semiconductorintegrated circuits produced at low cost which do not use copper-basedwiring, i.e., using only an aluminum-based wiring, or an aluminum-basedwiring combined with a tungsten-based wiring, and the like. Amanufacturer of semiconductor integrated circuits is required to meetdemands, such as this situation. In particular, in the ASIC (ApplicationSpecific Integrated Circuit) field of gate arrays, standard cells,embedded cell arrays, and the like, flexible production with lowercosts, which meet various customers' demands is desirable. In order tomeet these requirements, it is necessary to produce products which donot use copper-based wiring and to produce products which do use acopper-based wiring in a condition in which these two products mutuallycomplement and support each other.

In theory, in a gate array type ASIC, it is possible to produce aproduct to meet various customers' demands by using basic cells each ofwhich includes a predetermined number of transistors arranged in apredetermined shape. However, in reality, if the entire necessarycircuit blocks are developed after receiving orders from individualcustomers, the development time becomes longer and the development costbecomes higher. Furthermore, if a sufficient development time is notensured, it is difficult to develop a product with an acceptableperformance. In order to solve this problem, it is necessary to developin advance not only the basic cell but also circuit blocks to realizecommonly used finctions, such as an adder, a multiplier, SRAM, CPU, DSP,and the like, and to store these function blocks as macro cells. Whenreceiving an order from a customer, by selecting the appropriate macrocells, and combining them with a newly designed circuit blocks using thebasic cells, it is possible to shorten the development time and reducethe development cost. In other words, it is necessary to prepare a macrocell library comprising many macro cells that can be used in variousapplications with high performances in order to attain a highcompetitiveness and provide products which satisfy customers' variousdemands at lower development cost and with shorter development time.

In gate arrays, macro cells are formed using transistors in basic cells.Meanwhile, in standard cells and embedded cell arrays, macro cells areformed using individually designed transistors. In the standard cell andthe embedded cell array, the importance of a well-prepared macro celllibrary is even higher than the case of the gate array, because therequired function is primarily realized by combining the macro cells inthe library.

In order to develop a large number of macro cells for products with acopper-based wiring separately from those for products without acopper-based wiring, extra development time and costs will be incurred.Accordingly, it is preferable to use, as much as possible, the samemacro cell for both products with and without a copper-based wiring. Inreality, ASIC makers have been using the aluminum-based wiring as apremise, and have libraries comprising many macro cells designed andverified i.e., tested and confirmed that the cell has a sufficientperformance for the intended purpose, using the aluminum-based wiring asthe premise. Furthermore, in recent years, macro cells have come to bemore widely used in common as IPs (Intellectual Properties) amongmanufactures. By sharing macro cells with high performance, which manyusers need, interchangeability among manufactures and the convenience ofusers is improved and the burden of the macro cell development uponindividual manufactures is reduced. Therefore, it is desirable to usemacro cells designed and verified upon the premise of the aluminum-basedwiring i.e., without using a copper-based wiring in products with acopper-based wiring, while keeping the cost low, and utilizing the lowresistance and high electromigration tolerance of the copper-basedwiring. It is also desirable to keep compatibility of IPs among productswith and without a copper-based wiring.

The following discussion describes the considerations which are made todetermine whether and under what conditions in copper-based wiring ismost effectively utilized.

First, for the following reasons', use of the copper-based wiring forconnections within circuit blocks or macro cells is not very effective.

First, in a small-scale macro cell, even though the wiring resistance isreduced by replacing an aluminum-based wiring with a copper-basedwiring, performance is barely improved. The main reason is thatperformance is mainly determined by the performance of the transistorand the wiring capacitance. Meanwhile, in large-scale macro cells, thereare cases in which the wiring resistance influences the performance. Inmacro cells such as this, by replacing an aluminum-based wiring with acopper-based wiring, there is a possibility that performance can beimproved. However, as long as the macro cells are designed on thepremise of the aluminum-based wiring, there is a low possibility that asignificant performance improvement can be realized by simply replacingthe aluminum-based wiring with a copper-based wiring. In other words,various modifications and optimizations of the cell are needed tosignificantly improve performance by fully utilizing the advantages ofcopper-based wiring.

In addition, in order to implement copper-based wiring in macro cellswhich are designed on the premise of aluminum-based wiring, it isnecessary to fabricate test devices, evaluate the characteristics of thetest devices, and confirm that the necessary characteristics areobtained before using the macro cell in an actual product with acopper-based wiring. Although significant changes in the characteristicsare not anticipated from the differences in the wiring resistancebetween the aluminum-based wiring and the copper-based wiring, changesin the production process may result in unpredictable changes in thecharacteristics. The reason is that significant changes beyond just thechange of materials occur in the process by replacing the aluminum-basedwiring that uses an etching process with a copper-based wiring that usesthe damascene process.

Furthermore, it is known that copper produces a deep level in silicon.Because of this, there is a concern that copper atoms in the wiring maybe diffused in a transistor and the characteristics of the transistormay deteriorate. Needless to say, to prevent this phenomena, a diffusionbarrier layer comprising a titanium nitride film or the like can be usedin the formation of the copper-based wiring. However, a specialattention is needed when lower wiring layers close to transistors aremade with the copper-based wiring. Even though there may in reality beno problem of deterioration of the transistor due to the copperdiffusion, it is necessary to evaluate and confirm the influence of thecopper-based wiring upon the performance and reliability of thetransistor before it is actually used for a product. It normally takesseveral months or more to complete the evaluation.

Accordingly, unless a significant improvement in performance thatcompensates for the cost of carrying out this type of evaluation andconfirmation procedures, replacing aluminum-based wiring in a macro cellwith copper-based wiring has little value.

Needless to say, if the wiring dimensions are reduced on the premise oflow resistance and high electromigration tolerance of the copper-basedwiring, it is possible to reduce the macro cell area and improve theperformance. However, to implement this, it is necessary to newlyperform a mask design and to manufacture test devices and performoperation tests. In order to carry out these procedures, it usuallytakes several months or more. It is possible that only the importantmacro cells are re-designed and verified on the premise of thecopper-based wiring in order to make a smaller library for use inproducts with the copper-based wiring. However, it is not realistic tore-design and verify all of the macro cells in a library in order toimplement them into products with a copper-based wiring, because toomuch time and cost is needed.

On the other hand, significantly improved performance can be obtained byreplacing aluminum-based wiring with copper-based wiring in thefollowing applications:

1) Long-Distance Signal Wiring

For the wiring within a macro cell or other circuit blocks, the wiringdistance is merely from about 100 μm to about several mm. Meanwhile, thewiring between circuit blocks or between I/O cells, which carry outsignals to and/or carry in signals from the outside of the integratedcircuit, and circuit blocks has a length of the order of 1 mm or, insome cases, in the order of the chip dimensions of the integratedcircuit (1 cm or more). Wiring resistance and capacitance areproportional to the wiring length, so wiring for long distances, asdescribed above, produces a large resistance and capacitance. Thiscauses large signal delays and often limits the operational speed of theentire integrated circuit.

By reducing the wiring resistance by utilizing copper-based wiring withlow resistance for long distance signal wiring, or by reducing thewiring capacitance through decreasing the dimensions by utilizing thelow resistance of the copper-based wiring, it is possible to reducesignal delay and improve the operational speed of the integratedcircuit. Needless to say, for this type of long distance signal wiring,use of the copper-based wiring in combination with the wiring structuresof the invention, which reduces the capacitance between the wires and/orbetween wiring layers, further improves the operational speed.

2) Clock Wiring

Many circuit blocks within an integrated circuit operate synchronouslywith a common clock signal. However, the clock wiring, which distributesthis clock signal throughout the integrated circuit, is generally aslong as or even longer than the chip dimensions, i.e., about 1 cm ormore and has large resistance and capacitance. Therefore, due to thedelay of the clock signal in the clock wiring, a difference in the clocktiming (so-called “skew”) occurs when the clock signal is transmitted todifferent circuit blocks in an integrated circuit. As a result,synchronous operation may fail. When a larger margin is given in thetiming in order to ensure synchronous operation, the operational speeddeteriorates.

By reducing the resistance utilizing copper-based wiring and/or byreducing capacitance through the reduction of the wiring dimensions ofthe clock wiring, skew of the clock signal between the circuit blocksdisposed in various positions of a chip can be reduced. This can resultin an improvement of operational speed. Needless to say, for this clockwiring, the use of copper-based wiring in combination with the wiringstructures disclosed in this application to reduce the capacitancebetween the wires and between the wiring layers further improvesoperational speed.

3) Power Bus Wiring

In order to operate an integrated circuit, it is necessary to provideelectric power for all of the elements in the integrated circuit. Toprovide the electric power, wires are hierarchically provided, and thewires which are commonly provided in order to provide electric power formany elements in an integrated circuit is generally called power bus.For example, U.S. Pat. No. 4,511,914 discloses an example of a power buswhich is provided in a grid-like manner in order to provide power forbasic cells in a gate array. U.S. Pat. No. 5,040,144 discloses anexample of a power bus which is provided in a grid-like manner in orderto provide power for a memory cell array.

Such power bus wiring has a length of the order or more than the chipdimension, i.e., 1 cm or more. Furthermore, in order to provide electricpower for many elements, a large amount of direct current, moreaccurately, pulsating current flows. Because of this, there is a highpossibility that electromigration failure may occur. Moreover, when manyelements operate simultaneously, a large voltage drop may occur due tothe resistance of the bus wiring thus resulting in operation failure.

Use of copper-based wiring with low resistance and high electromigrationtolerance as power bus wiring has a significant effect to solve theseproblems.

In conventional integrated circuits, multilevel wiring, including two ormore wiring layers, is commonly used. For the connection within circuitblocks, such as macro cells, first and second aluminum-based wiringlayers including wires that cross in mutually orthogonal directions, forexample, are mainly used. Wires in these wiring layers are mainly usedto connect between transistors within a circuit block. In some cases,one or more additional aluminum-based wiring layers are further providedon these wiring layers.

Accordingly, it is possible to use, for example, two aluminum-basedwiring layers, which are used to make connections within the macro cellas they are, and add one or more layers of the copper-based wiring. Thecopper-based wiring can be preferably used for the long-distance signalwiring, clock wiring, power bus wiring, or the like.

When macro cells use more than two aluminum-based wiring layers, it ispossible to use these wiring layers as they are, and add one or morecopper-based wiring layers on top of these layers. When the upper-mostaluminum-based wiring layer or layers, for example, the third wiringlayer, is mainly used for limited purposes, for example, for theconnection between circuit blocks within a macro cell, it is possible toreplace this wiring layer with a copper-based wiring layer. If only theupper-most wiring layer or layers remote from the transistor arereplaced with a copper-based wiring layer or layers, the possibility ofdegradation of the transistor due to the diffusion of copper is small.

FIGS. 26A and 26B are cross-sectional views of one example of a wiringlayer structure for products without and with a copper-based wiring,respectively. FIG. 26A is a wiring layer structure without acopper-based wiring. Above the surface of a silicon substrate 10, first,second, and third aluminum-based wiring layers, 106, 108, and 110 areformed in order from the bottom. Interlayer dielectric layers are formedbetween the silicon substrate 10 and the first wiring layer 106, andbetween the respective wiring layers. Under the first aluminum-basedwiring layer 106, a tungsten-based wiring layer, for example, may beprovided. In order to connect within respective circuit blocks, closelyspaced wires formed in mutually orthogonal directions in the twoaluminum-based wiring layers 106 and 108 are mainly used. The thirdaluminum-based wiring layer 110 is mainly used, for example, to formsignal wiring with long distances between circuit blocks, power buswiring, clock wiring, and the like. It is preferable for these types ofwiring to have low wiring resistance and capacitance. Accordingly, incomparison to the wires within the respective circuit blocks which areformed on the first and second aluminum-based wiring layers, the widthand space of the wires on the third wiring layer are enlarged.Furthermore, in order to reduce the wiring resistance, in comparison tothe wires on the first and second wiring layers, the height of thewires, i.e., film thickness of the metal film which is used for theformation of the wiring is increased. Such wide and thick wires areoften referred to as “fat wires”.

Meanwhile, a product with a copper-based wiring has a wiring layerstructure, for example, as shown in FIG. 26B. That is, the first andsecond aluminum-based wiring layers 106 and 108 are used as they are,and the third aluminum-based wiring layer is replaced with a firstcopper-based wiring layer 112. Further, a second copper-based wiringlayer 114 is added. The wiring within respective circuit blocks isformed as in the case of the product without a copper-based wiring. Thatis, the same mask pattern is used as is used for the product without acopper-based wiring. Needless to say, fine corrections and improvementsare made as needed. Using the first and second copper-based wiringlayers 112 and 114, the long distance signal wiring between the circuitblocks, power bus wiring, clock wiring, and the like are formed.

Needless to say, the second copper-based wiring layer 114 is notnecessary if merely replacing the third aluminum-based wiring layer ofFIG. 26A. However, for example, in order to manufacture high performanceproducts by making the best use of the lower resistance copper-basedwiring for the long distance signal wiring, it is effective to providetwo copper-based wiring layers and improve the degree of freedom of theconnection in the mutually orthogonal directions. As needed, it ispossible to provide three or more copper-based wiring layers.Conversely, there are cases in which it is possible to reduce the numberof wiring layers by using the copper-based wiring and thereby to reduceproduction costs. For example, if the dimensions of the wires aredecreased and the density of the wires is increased by the premise ofthe low resistance and high electromigration tolerance of thecopper-based wiring, there are instances where two aluminum-based wiringlayers, for example, the third and fourth wiring layers, can be replacedwith one copper-based wiring layer.

FIG. 27 shows an example of signal wiring over a long distance. Aplurality of circuit blocks 118 are arranged on a semiconductorintegrated circuit chip 116 and a plurality of I/O cells 120 arearranged on the periphery. Moreover, to perform signal communicationbetween the circuit blocks 118, a long distance signal wiring 122 isprovided. A long distance signal wiring 124 is further provided toperform signal exchange with devices outside of the semiconductorintegrated circuit to the respective circuit blocks 118. In this Figure,each wiring is denoted as one line, but, for example, to transmit asignal with 32 bits, 32 wires of the wiring are actually provided.

FIG. 28 shows an example of the clock wiring. A plurality of circuitblocks 126 are arranged on the semiconductor integrated circuit chip116. Furthermore, an oscillator 128 for generating a clock signal isarranged at the center of the chip. From this oscillator 128, the clocksignal is distributed to the respective circuit blocks 126 through ahierarchy provided by clock wiring 130. That is, the clock signal isfirst distributed through wires directly connected to the oscillator,and then distributed through branch wires to respective circuit blocks.Within the respective circuit block, a lower level wiring (not shown) isprovided to further distribute the clock signal to respective gates inthe circuit block. The copper-based wiring is particularly effective toform the higher level portion of the hierarchically provided clockwiring, that is, the portion provided to distribute the clock signalfrom an oscillator, or from a pad for receiving the clock signal, to aplurality of circuit blocks.

As described above, in the semiconductor integrated circuit according tothe invention, a macro cell which was designed and verified on thepremise of the aluminum-based wiring, i.e., without using thecopper-based wiring, is used as it is. And high performance can berealized by taking advantage of the low resistance and highelectromigration tolerance of the copper-based wiring. In addition, thepossibility of degradation of transistors due to the copper diffusionfrom the copper-based wiring is low because the lower wiring layersarranged adjacent to the transistors are aluminum-based wiring layers,just as in the conventional integrated circuits.

As a result, it is possible to maintain the compatibility of IPs. Thatis, for example, IPs designed on the premise of aluminum-based wiringcan be used both in products with and without a copper-based wiringwithout requiring substantial modifications.

Furthermore, in comparison with cases where copper-based wiring layersare used as the lower wiring layers, it is possible to reduce thethickness of the diffusion barrier layer that is arranged in order toprevent copper diffusion, or to simplify the process of forming thediffusion barrier layer. Furthermore, it is possible to simplify thetest procedures to evaluate the influence of the copper-based wiring.That is, it is sufficient to perform a test only concerning theinfluence of the copper diffusion on the transistor characteristics,using limited types of test devices with a copper-based wiring providedin the third layer, for example. The wires in the internal part of themacro cell are still made on aluminum-based wiring layers, so a testregarding the characteristic changes of the individual macro cells dueto the use of copper-based wiring can be omitted. Furthermore, byproviding a plurality of copper-based wiring layers and using each ofthem mainly for specific purposes, it is possible to further improve thedegree of freedom of the wiring and improve the performance of theintegrated circuit. Specifically, in order to form long distance signalwiring, it is preferable to provide a pair of copper-based wiringlayers, or to provide two or more pairs of copper-based wiring layers,in order to form wires in mutually orthogonal directions with a highdegree of freedom.

Among the power bus wiring, in many cases, portions that are low (deep)in the hierarchy are formed in lower wiring layers which are also usedfor the connections between transistors within macro cells. It ispossible to use these lower wiring layers as they are and to add one ormore copper-based wiring layers on top of these aluminum-base wiringlayers. Wires disposed generally parallel to and electrically connectedin parallel to the wires in the power bus wiring can be formed on thesecopper-based wiring layers. By so doing, it is possible to improve thecurrent conduction capability of the power bus wiring by utilizing thelow resistance and high electromigration tolerance of the copper-basedwiring. As a result, stability of the operation can be improved becauseof the reduction of the voltage drop in the bus wiring, andelectromigration reliability can be improved. In other words, it ispossible to use copper-based wiring for the purpose of reinforcing thealuminum-based wiring. It is possible to provide a wire on acopper-based wiring layer for each of the corresponding wires on analuminum-based wiring layer. It also possible to provide a common wirein a copper-based wiring layer for two or more corresponding wires in analuminum-based wiring layer. Meanwhile, portions that are high (shallow)in the hierarchy of the power bus wiring, for example, the portionsurrounding the periphery of a semiconductor chip for providing theelectric power for substantial portion of the integrated circuit, has along length. In addition, these portions of the power bus wiring shouldhave a capability to flow a large amount of current. These portions ofthe power bus wiring are particularly suited to be formed on one or morecopper-based wiring layers. Furthermore, it is effective to provideseparate copper-based wiring layers for the power potential (VVD) andground potential (VSS) power bus wiring, respectively.

FIG. 29 shows an example of the power bus wiring. The Figure shows apower bus with a three level hierarchy which is provided in a gate arraytype semiconductor integrated circuit. At the periphery of theintegrated circuit chip 116 are arranged I/O cells 120, and in theinternal region a cell array 132 is arranged in which many basic cellshaving a specific width and height are arranged in columns and rows. TheFigure also shows the power bus wiring providing electric power for thebasic cells. The primary power bus 134 is arranged so as to surround theentire cell array. The primary power bus supplies electric power to asubstantial portion of the integrated circuit, that is, all of the basiccells. For other portions of the integrated circuit, such as I/O cells,a separate power bus wiring may be provided. The third level power buses138 are arranged on respective rows of the basic cells in order tosupply electric power for the transistors in the basic cells of the row.The second level power buses 136 are arranged so as to link between theopposite arms of the primary power bus, and are respectively connectedto the third level power buses. The second level power buses decreasethe impedance between the primary and third level power buses, anddecreases the voltage drop which occurs when the transistors in manybasic cells operate simultaneously.

In a product with a copper-based wiring, higher level portions of thepower bus, for example, the primary power bus 134 and secondary powerbuses 136, are formed on one or more copper-based wiring layers.Meanwhile, lower level portions, for example, the third power buses 138,are formed on the aluminum-based wiring layers. Needless to say, wiringto reinforce the third level power buses 136 can be also provided in thecopper-based wiring layers.

In the Figure, only one wire or one group of wires is shown for each ofthe levels. In reality, however, two or more groups of wires are usuallyprovided each for supplying, for example, VDD and VSS electricpotential.

Furthermore, in addition to forming the necessary numbers ofcopper-based wiring layers, it is possible to add another aluminum-basedwiring layers. For example, for the top-most wiring layer, it ispreferable to use an aluminum-based wiring layer because it has a provenhistory in connection to the package by the bonding. As for the top-mostwiring layer, it is also preferable to use gold-based wiring because ithas superior corrosion resistance and decreases the risk of degradationof the integrated circuit due to the exposure to the operationenvironment.

As described above, the following advantages can be obtained in productswith a copper-based wiring by using macro cells selected from the samelibrary which is prepared for the products without a copper-basedwiring, using aluminum-based wiring layers used in the connectionswithin the macro cell as they are, and adding one or more copper-basedwiring layers on top of the aluminum-based wiring layers.

Higher performance can be realized by using copper-based wiring forwires of a selected type for wiring whereby the lower resistance andhigh electromigration tolerance of the copper-based wiring can be takenadvantage of. The selected type of wiring includes long distance signalwiring, clock wiring, power bus wiring and the like.

By using the same macro cell library, it is possible to take advantagesof the investment of the macro cell library developed on the premise ofthe aluminum-based wiring, and to reduce the development time and cost.

It is possible to maintain the compatibility of IPs shared with othermanufactures and to improve the performance of integrated circuitproducts as a whole.

Due to the above advantages, it is possible to provide products withhigh performance with a short development time and at low developmentcost.

In reality, providing a product as described above with copper-basedwiring as a high performance grade product meets the demands ofcustomers for whom performance is the primary concern. Meanwhile,providing a product without a copper-based wiring as a standard gradeproduct meets the demands of the customers for whom cost is the primaryconcern. The macro cell library is commonly used for high performancegrade products and standard grade products. Furthermore, both gradeproducts are to be commonly manufactured as much as possible, with theexception of the copper-based wiring processes, including the grooveforming process and the like for the damascene method, wherebymanufacturing cost reduction is achieved. For example, the process forforming basic cells is used in common, and the same manufacturing linecan be used for the common process steps.

In designing a product of the standard grade, necessary macro cells areselected from the library and placed on a semiconductor integratedcircuit chip. The macro cell includes wires necessary to makeconnections within the macro cell. Further, connections outside of themacro cells are also made using aluminum-based wiring layers.

Similarly, in designing a product of the high performance grade,necessary macro cells are selected from the library and placed on achip. Portions of wires within the macro cell formed on lower wiringlayers are used as they are. That is, these portions of the wires areformed on one or more aluminum-based wiring layers. Only portions ofwires formed on higher wiring layers are replaced by wires on one ormore copper-based wiring layers. As a result, connections within themacro cells are mainly made by wires on aluminum-base wiring layers.Further, connections outside of the macro cells are made mainly usingwires on one or more copper-based wiring layers. The wires for theconnections outside of the macro cells include wires of selected typesof wiring that can take advantages of the copper-based wiring with lowresistance and high electromigration tolerance. For example, longdistance signal wiring between the macro cells and between the macrocells and the I/O cells, a power bus wiring, especially, high levelportions of the hierarchically provide power bus, and a clock wiring,especially, portions of the clock wiring provided for delivering theclock signal to a plurality of circuit blocks, and the like are made onthe copper-based wiring layer. As a result, higher performance can berealized by making the use of the copper-based wiring, even though themacro cells are selected from the common library of uses. Modificationsto the macro cells can be made as needed. However, a substantialmodification or re-design should be avoided to minimize developmentcosts.

These designing procedures are made on a CAD (computer aided design)system. The CAD system produces a mask data that is used to make masks.And semiconductor integrated circuits are produced using the masks.

By using the aluminum-based wiring layers at the lower side incombination with the copper-based wiring layers at the upper side, thefollowing advantages, for example, can be obtained, even in a productwhich was not originally developed using copper-based wiring as apremise:

1) Developed on the premise of aluminum-based wiring, copper-basedwiring layers can be used as countermeasures in a case that, forexample, the number of wires, such as the power bus wires, is too largeto be accommodated within a predetermined maximum chip size. In thiscase, if a copper-based wiring is not usable, it is necessary tore-design from the beginning to reduce the number of wires or to adapt alarger and more expensive package. The larger package may necessitatethe re-design of the circuit board. Even in this case, if copper-basedwiring is usable, it is possible to accommodate the necessary number ofwires within the predetermined chip size by replacing one or more upperaluminum-based wiring layers with one or more copper-based wiringlayers. By utilizing the low resistance and high electromigrationtolerance of the copper-based wiring, the dimensions of the wiring canbe reduced and the necessary number of wires can be accommodated withinthe predetermined chip size. Although the manufacturing cost of thecopper-based wiring itself is higher than that of the aluminum-basedwiring, it is possible to reduce the overall cost, including thedevelopment cost, as compared to the instance where redesigning from thebeginning or adaptation of a larger package is necessary.

2) After developing a semiconductor integrated circuit with certainfunctions without using copper-based wiring because of the costconsideration, it is possible to promptly respond to a request from acustomer to improve the performance of the integrated circuit. That is,it is possible to easily improve the performance without makingsignificant changes to the circuit or layout of the originally developedproduct by adding copper-based wiring layers on top of thealuminum-based wiring layers, or by replacing the higher aluminum-basedwiring layers with copper-based wiring layers. The copper-based wiringlayers are mainly used to form wires which have large impacts on theperformance of the integrated circuit, such as long distance signalwiring and the like. If all of the aluminum-based wiring layers arereplaced with copper-based wiring layers and integrated circuits arere-designed on the premise of copper-based wiring, even more significantperformance improvements can be expected. However, in order to carrythis out, a longer development time is necessary, and development costsmay also increase.

The above description used the example of ASIC products, such as gatearrays, standard cells, embedded cell arrays, and the like, anddescribed the effects of manufacturing semiconductor integrated circuitsusing aluminum-based wiring layers at the lower side in combination withcopper-based wiring layers at the upper side. However, in manysemiconductor integrated circuits, not limited to the ASIC products,there is a strong demand for the high performance, short developmenttime, and low development cost. Therefore, jointly using aluminum-basedwiring layers at the lower side and copper-based wiring layers at theupper layer side in this manner is advantageous for various kinds ofsemiconductor integrated circuits.

For example, in the FPGA (field programmable gate array) product, whichis one kind of the ASIC products, the same type of joint use of thealuminum-based wiring and copper-based wiring is advantageous. In thiscase, the programmable logic blocks and programmable wiring between theprogrammable logic blocks and between the programmable logic blocks andthe I/O cells of the FPGA corresponds to the circuit blocks and the longdistance wiring described above, respectively. That is, internalconnections within the respective programmable logic blocks would beformed mainly using aluminum-based wiring layers of the lower side, andthe programmable wiring between the programmable logic blocks andbetween the programmable logic blocks and I/O cells would be formedusing copper-based wiring layers of the upper side. Thus, theoperational speed of FPGA, which is mainly determined by the longdistance wiring, can be improved. Similar effects can be obtained byusing copper-based wiring for the clock wiring and the power bus wiring.

FIG. 30 shows an example of using the copper-based wiring for thesemiconductor integrated circuit that combines a DRAM (Dynamic RandomAccess Memory) and a logic circuit on the same chip. DRAM 144 includesmemory cell arrays 140 and a sense amplifier array 142, and logiccircuit block 146, for example, for performing image processing, arearranged on a semiconductor integrated circuit chip 116. To transmit asignal between the DRAM 144 and the logic block 146, data wiring 148,including a predetermined number of (for example, 256, 512 or 1024) datawires are arranged.

To perform image processing, a large capacity memory is needed totemporarily store a large volume of data. Furthermore, for example, toperform realtime moving image processing, it is necessary to transmit alarge volume of image data between the image processing circuit and thememory in a short period of time. It is effective to use copper-basedwiring with lower resistance for this purpose.

In order to reduce cost, it is preferable to manufacture the memory cellarrays 140 using the same manufacturing process as is used for memorycell arrays of a conventional or stand-alone DRAM product. For thewiring of the memory cell array of the stand-alone DRAM, only two wiringlayers are usually used. Therefore, by forming the wiring of this partwith conventional aluminum-based wiring and providing a copper-basedwiring layer on top of this and forming the data wiring 148 in thiswiring layer, it is possible to improve the compatibility of themanufacturing process with processes associated with conventional DRAMproducts. Furthermore, since the lower wiring layers, which are close tothe memory cells, are aluminum wiring layers, it is possible to preventdegradation of the memory cells, which are extremely sensitive to thecontamination, due to the copper diffusion.

It is also effective to use the copper-based wiring for similar datawiring for transmitting data at high speed between a CPU (CentralProcessing Unit) and cache memory, for example, in a microprocessor.

As described above, the product without a copper-based wiring isprovided for customers who need lower cost, and a product with acopper-based wiring is provided for customers who need higherperformance. In addition, if the copper-based wiring is used only forthe higher wiring layers, and if the copper-based wiring is used only inhigher-grade products, the necessary production capacity for thecopper-based wiring formation processes is small relative to thecapability for the processes commonly used both for the products withand without a copper-based wiring. Therefore, it is possible to use thecopper-based wiring formation facilities in common with a plurality ofproduction lines for other processes, including transistor formation andaluminum-based wiring formation. Furthermore, when a new factory withcopper-based wiring formation facilities is built, the facilities of thenew factory can be used in common with a plurality of existent factorieswithout copper-based wiring formation facilities. In this way, totalinvestment costs can be reduced.

FIGS. 25A, 25B, and 25C are cross-sectional views showing the formingprocesses for a wiring structure according to an eighth embodiment ofthe invention.

As shown in FIG. 25A, and in the same manner as described in connectionwith the fourth embodiment, a first wiring layer including wires 18 a,18 b, and 18 c is formed on an underlying dielectric layer 12 on asemiconductor substrate 10. Surface portions of the underlyingdielectric layer 12 between the wires of the first wiring layer 18 areremoved to a depth of d1. After this, an underlying film 26 is formedand a precursor of, for example, fluorinated polyimide is applied, and afluorinated polyimide film is formed by heat curing. Furthermore, thesurface of the fluorinated polyimide film is planarized by, for example,CMP. Thus, a low dielectric constant film 28 made of the fluorinatedpolyimide is formed between and on the wires of the first wiring layer18. The thickness of the low dielectric constant film 28 on the top ofthe wires is t3. The thermal conductivity of the low dielectric constantfilm 28 made of fluorinated polyimide is about 0.24 W/mK at roomtemperature, which is about ⅙ of that of silicon oxide (about 1.4 W/mKat room temperature). The film thickness of the low dielectric constantfilm 28 on the wires of the first wiring layer 18 is thin in comparisonto the fourth embodiment. The space between the wires of the firstwiring layer 18 is s1, and the film thickness of the underlying film 26on the top surface of the wires is t2.

Next, as shown in FIG. 25B, a silicon nitride film is deposited, forexample, by plasma CVD, and a heat conductive insulating film 100 isformed. The thickness of the heat conductive insulating film is t4. Thethermal conductivity of silicon nitride is about 19 W/mK at roomtemperature, which is about 14 times higher than that of silicon oxide.A film including insulating material of a higher thermal conductivity,as described, than silicon oxide is referred to hereafter as a “heatconductive insulating film.” After this, a second low dielectricconstant film 102 is formed, and, for example, by depositing afluorinated silicon oxide film, a cap film 30 is formed. The thicknessof the second low dielectric constant film 102 and the cap film 30 is t5and t6, respectively. By the process described above, an interlayerdielectric layer 104, including the underlying film 26, the lowdielectric constant film 28, the heat conductive insulating film 100,the second low dielectric constant film 102, and the cap film 30, isformed.

After the process described above, via holes are formed in theinterlayer dielectric layer 104, and plugs (not shown) are formed.Furthermore, the same process is repeated as needed, and the second andsubsequent wiring layers and interlayer dielectric layers are formed.FIG. 25C shows a cross-sectional view of a structure in which the secondwiring layer 22 is formed.

After that, a passivation layer and bonding pads are formed, and thewafer manufacturing process for the semiconductor integrated circuit iscompleted.

In the wiring structure of the fourth embodiment, the interlayerdielectric layer is mainly formed with a film of a low dielectricconstant material which has low thermal conductivity. In this type ofstructure, during an electromigration test, the problem of wiretemperature rising during the test due to Joule heat in the wire and anelectromigration failure occurs rapidly (for example, see K. Banerjee etal., International Electron Devices Meeting, Digest of Technical Papers(1996) p. 65). In contrast, in the wiring structure according to thisembodiment, part of the interlayer dielectric layer is formed with aheat conductive insulating film comprising silicon nitride. Since heatdissipates through the heat conductive insulating film, localtemperature rise of the wires due to Joule heat is suppressed, thusimproving the reliability of the wiring.

In order to increase the effect of suppressing local temperature rise,it is preferable to position the heat conductive insulating film 100close to the wires of the first wiring layer 18. On the other hand, toreduce capacitance between wires of the first wiring layer 18, it ispreferable to separate the heat conductive insulating film 100 from thewires. This is because the dielectric constant of silicon nitride ishigh (about 7.5). In most cases, the length of the wire which generatesJoule heat is in the order of 100 μm or more, while the distance betweenthe wire and the heat conductive insulating film 100 (that is, thedistance from the top surface of the wires of the first wiring layer 18to the bottom surface of the heat conductive insulating film 100measured in the perpendicular direction with respect to the main surfaceof the semiconductor substrate 10, or in other words, t2+t3) is only inthe order of 1 μm. Because of this, in practice, the effects ofsuppressing local temperature rise do not significantly depend on thedistance between the heat conductive insulating film 100 and the wiresof the first wiring layer 18. Therefore, the distance between the heatconductive insulating film 100 and the wires of the first wiring layer18 should be determined so that the capacitance between the wires isreduced. Specifically, it is recommended for (t2+t3) to be selected tobe about 20% or more, and preferably to be about 50% or more of s1. Itis recommended that (t5+t6) be selected to be about 20% or more, andpreferably be about 50% or more of s11.

Furthermore, in order to reduce the capacitance between wiring layers,it is preferable to have a large (t3+t5) value. Specifically, if (t3+t5)is made about the same or more, and preferably about twice or more asthe larger one of s1 and s11, the influence of the capacitance betweenthe wiring layers becomes small compared to the influence of thecapacitance between wires within the same wiring layer.

Furthermore, in order to improve the effect of suppressing localtemperature rise, it is preferable to increase the thickness of the heatconductive insulating film 100. However, if it is too thick, the aspectratio of the via holes, i.e., the ratio between the depth and openingdimensions, which connect between the wiring layers, increases. The viaconnection yield also decreases. In practice, a thickness of about thesame or more, and preferably, about twice or more as the value of(t2+t3) is recommended.

In this embodiment, a silicon nitride film is used as the heatconductive insulating film 100, but the invention is not limited tothis. For example, it is also possible to use an aluminium oxide(alumina) film. Alumina has a thermal conductivity of 21 W/mK at roomtemperature, which is about 15 times of that of silicon oxide. It isalso possible to use any film comprising a material having a thermalconductivity higher than that of silicon oxide; preferably about threetimes or more, and more preferably about five times or more of that ofsilicon oxide. Furthermore, a significant effect can be obtained whenthe heat conductive insulating film 100 is formed by using a materialhaving a thermal conductivity that is about ten times or more than thatof the silicon oxide.

This embodiment shows an example of forming the low dielectric constantfilm 28 with fluorinated polyimide, but the invention is not limited tothis method. It is possible to use various kinds of low dielectricconstant materials. The thermal conductivity of these materials varies,depending upon the material, but in many cases, it is significantlylower than that of silicon oxide. The effects of the invention aresignificant when the low dielectric constant films 28 and 102 are formedusing a material having a thermal conductivity of about ⅓ or less thanthat of the silicon oxide. Furthermore, particularly significant effectscan be obtained when a material having a thermal conductivity of about ⅕or less of that of the silicon oxide is used.

The wiring structure, the method of forming the wiring structure, and asemiconductor integrated circuit which applies the wiring structureaccording to the invention is explained in detail above, but the presentinvention is not limited to the embodiments described above. Needless tosay, various improvements and alternatives may be made without departingfrom the scope of the invention.

As described above in detail, various wiring structures and methods offorming the wiring structure are provided to effectively reduce thewiring capacitance and to improve the operational speed of semiconductorintegrated circuits.

Specifically, according to one aspect of the present invention, a lowdielectric constant film having a dielectric constant lower than that ofsilicon oxide is formed between wires in a wiring layer. The lowdielectric constant film contacts side surfaces of the wires and a lowerlevel of the low dielectric constant film between the wires is lowerthan a bottom level of the wires. As a result, the electric fieldbetween the wires is effectively confined within the low dielectricconstant film and the capacitance between the wires is effectivelyreduced. Specific materials and deposition methods are preferably usedto form the low dielectric constant film to allow contact of the lowdielectric constant film to the side surfaces of the wires.

According to another aspect of the invention, an interlayer dielectriclayer includes an underlying film having a dielectric constant lowerthan that of silicon oxide and a low dielectric constant film having adielectric constant lower than that of the underlying film formedbetween the wires. The underlying film allows the use of a materialhaving a very low dielectric constant to form the low dielectricconstant film. Further the wiring capacitance is effectively reducedsince the dielectric constant of the underlying film is lower than thatof ordinary silicon oxide. A specific material and deposition method arepreferably used to form the underlying film to improve, for example, theability to suppress water diffusion from the low dielectric constantfilm to the wires.

According to another aspect of the invention, an interlayer dielectriclayer includes an underlying film and a low dielectric constant filmhaving a dielectric constant lower than that of silicon oxide, wheresurfaces of the underlying film on side surfaces of the wires arepositively sloped. The positive slope facilitates the filling of narrowspaces between the wires with the low dielectric constant film. Aspecific material and deposition method are preferably used to form thepositively sloped underlying film. A specific method to form the lowdielectric constant film can be preferably combined to enhance thefilling.

According to another aspect of the invention, an interlayer dielectriclayer includes an underlying film and a low dielectric constant filmhaving a dielectric constant lower than that of silicon oxide, and athickness of the underlying film on upper portions is smaller than thaton lower portions. The smaller thickness on the upper portionsfacilitates the filling of narrow spaces between the wires with the lowdielectric constant film. A specific material and a deposition methodare preferably used to form the underlying film. A specific method offorming the low dielectric constant film can be preferably combined toenhance the filling.

While the above mentioned wiring structures can preferably be used withwiring formed by an etching method, the following structures canpreferably be used with the wiring formed by the damascene method.

According to another aspect of the invention, an intra-layer dielectriclayer includes a low dielectric constant film having a groove in which awire will be formed, and side wall films having a dielectric constantlower than that of silicon oxide are formed on side walls of the groove.The side wall film allows use of materials having a very low dielectricconstant to form the low dielectric constant film. Because of the lowdielectric constants of the side wall films and the low dielectricconstant film, the capacitance between the wires is effectively reduced.A specific material and deposition method are preferably used to formthe underlying film to improve, for example, the ability to suppresswater diffusion from the low dielectric constant film to the wires.

According to another aspect of the invention, an intra-layer dielectriclayer includes a low dielectric constant film having a groove in which awire will be formed, and side wall films having positively slopedsurfaces are formed on side walls of the groove. The positively slopedsurfaces of the side wall films facilitate the filling of narrow grooveswith a metal film to form the wiring. A specific material and depositionmethod are preferably used to form the positively sloped side wallfilms. A specific method for forming the metal film can be preferablycombined to enhance the filling.

According to another aspect of the invention, an intra-layer dielectriclayer includes a low dielectric constant film having a groove in which awire will be formed, and side wall films having a smaller thickness onupper portions than that on lower portions. The smaller thickness of theside wall films on the upper portions facilitates the filling of narrowgrooves with a metal film to form the wiring. A specific material and adeposition method are preferably used to form the side wall films havinga smaller thickness on the upper portions. A specific method for formingthe metal film can be preferably combined to enhance the filling.

On the other hand, the semiconductor integrated circuit according to theinvention utilizes the advantages of a low resistance wiring, such as acopper-based wiring, while the difficulties of the low resistance wiringare effectively overcome.

Specifically, according to one aspect of the present invention, asemiconductor integrated circuit includes at least one aluminum-basedwiring, at least one low resistance wiring layer disposed over the atleast one aluminum-based wiring, and at least one circuit blockincluding transistors connected with each other by wires in the at leastone aluminum-based wiring layer. Wires of a selected type of wiring areformed on the at least one low resistance wiring layer. The advantagesof the low resistance wiring are fully utilized because wires havinglower resistance and high electromigration tolerance of the lowresistance wiring can be integrated and formed on the low resistancewiring layer. In addition, since aluminum-based wiring is formed on thelower sides, negative effects caused by the diffusion of low resistancemetal can be effectively avoided.

According to another aspect of the present invention, a semiconductorintegrated circuit includes at least one aluminum-based wiring layer, atleast one low resistance wiring layer disposed over the at least onealuminum-based wiring layer, and at least one macro cell which has beendesigned and verified without using a low resistance wiring. Since macrocells designed and verified on the premise of aluminum-based wiring areused as they are in products with a low resistance wiring layer, thedevelopment costs of a product with a low resistance wiring layer isminimized. Further, compatibility of IPs is maintained.

According to another aspect of the invention, an application specificsemiconductor integrated circuit of one of a first and a second gradeincludes at least one macro cell selected from a macro cell librarycommonly provided for the first and the second grade, and at least onealuminum-based wiring layer. The semiconductor integrated circuitfurther includes at least one low resistance wiring layer only when thegrade is a preselected one. By providing a product with a low resistancewiring as a high performance grade product and a product without a lowresistance wiring as a standard grade products, various customers'demands are met. Further, by providing a common macro cell library forthe products of the both grades, development costs can be minimized.

What is claimed is:
 1. A semiconductor integrated circuit, comprising: asemiconductor substrate; at least one low resistance wiring layerdisposed over the semiconductor substrate, a plurality of fat wiresbeing formed in the at least one low resistance wiring layer; and analuminum-based wiring layer disposed over the at least one lowresistance wiring layer, the at least one low resistance wiring layerformed of a different material from, and having a lower resistance than,the aluminum-based wiring layer, wherein the semiconductor integratedcircuit includes a number of the at least one low resistance wiringlayer that is sufficient to provide a necessary degree of freedom ofconnection in mutually orthogonal directions.
 2. The semiconductorintegrated circuit according to claim 1, wherein the integrated circuithas a package and the aluminum-based wiring layer is used in connectionto the package.
 3. The semiconductor integrated circuit according toclaim 1, wherein the at least one low resistance wiring layer is acopper-based wiring layer.
 4. The semiconductor integrated circuitaccording to claim 1, further comprising at least one—intra-layerdielectric layer including a low dielectric constant film having adielectric constant lower than that of silicon oxide over thesemiconductor substrate, the intra-layer dielectric layer having aplurality of grooves formed in the low dielectric constant film, whereinthe plurality of fat wires are embedded within respective grooves in theintra-layer dielectric layer.
 5. The semiconductor integrated circuitaccording to claim 1, wherein the at least one low resistance wiringlayer is formed by a damascene method and the aluminum-based wiringlayer is formed by an etching method.
 6. A semiconductor integratedcircuit, comprising: a semiconductor substrate; at least one lowresistance wiring layer disposed over the semiconductor substrate, aplurality of low resistance wires being formed in the at least one lowresistance wiring layer; and an aluminum-based wiring layer disposedover the at least one low resistance wiring layer, the at least one lowresistance wiring layer formed of a different material from, and havinga lower resistance than, the aluminum-based wiring layer, wherein thesemiconductor integrated circuit includes a number of the at least onelow resistance wiring layer that is sufficient to provide a necessarydegree of freedom of connection in mutually orthogonal directions, andthe plurality of low resistance wires are used in a selected type ofwiring including at least one of: 1) a long distance signal wiring toconnect a circuit block to an I/O cell or to a second circuit block; 2)a high level portion of a hierarchically provided power bus wiring; and3) a portion of a clock wiring provided for delivering a clock signal toa plurality of circuit blocks.
 7. The semiconductor integrated circuitaccording to claim 6, wherein the integrated circuit has a package andthe aluminum-based wiring layer is used in connection to the package. 8.The semiconductor integrated circuit according to claim 6, furthercomprising at least one intra-layer dielectric layer including a lowdielectric constant film having a dielectric constant lower than that ofsilicon oxide over the semiconductor substrate, the intra-layerdielectric layer having a plurality of grooves formed in the lowdielectric constant film, wherein the plurality of low resistance wiresare embedded within respective grooves in the intra-layer dielectriclayer.
 9. The semiconductor integrated circuit according to claim 6,wherein the at least one low resistance wiring layer is formed by adamascene method and the aluminum-based wiring layer is formed by anetching method.
 10. A method of forming a semiconductor integratedcircuit having a package, comprising the steps of: forming fat wires inat least one low resistance wiring layer disposed over a semiconductorsubstrate, a number of the at least one low resistance wiring layer issufficient to provide a necessary degree of freedom of connection inmutually orthogonal directions; and adding an aluminum-based wiringlayer over the at least one low resistance wiring layer to use inconnection to a package, the at least one low resistance wiring layerformed of a different material from, and having a lower resistance than,the aluminum-based wiring layer.
 11. The method according to claim 10,further comprising forming at least one intra-layer dielectric layerincluding a low dielectric constant film having a dielectric constantlower than that of silicon oxide over the semiconductor substrate, theintra-layer dielectric layer having a plurality of grooves formed in thelow dielectric constant film, wherein the fat wires are formed to beembedded within respective grooves in the intra-layer dielectric layer.12. The method according to claim 10, wherein the at least one lowresistance wiring layer is formed by a damascene method and thealuminum-based wiring layer is formed by an etching method.